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参数资料
| 型号： | M5LV-128/74-15VI |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 38/42页 |
| 文件大小： | 0K |
| 描述： | IC CPLD 128MC 74I/O 100TQFP |
| 标准包装： | 90 |
| 系列： | MACH® 5 |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 15.0ns |
| 电压电源 - 内部： | 3 V ~ 3.6 V |
| 宏单元数： | 128 |
| 输入/输出数： | 74 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 托盘 |
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MACH 5 Family
5
Product-Term Array and Logic Allocator
The product-term array uses the same sum-of-products architecture as PAL devices and consists of 32 inputs
(plus their complements) and 64 product terms arranged in 16
clusters. A cluster is a sum-of-products
function with either 3 of 4 product terms.
Logic allocators assign the clusters to macrocells. Each macrocell can accept up to eight clusters of three or
four product terms, but a given cluster can only be steered to one macrocell (Table 4). If only three product
terms in a cluster are steered, the fourth can be used as an input to an XOR gate for separate logic generation
and/or polarity control.
The
wide logic allocator is comprised of all 16 of the individual logic allocators and acts as an output switch
matrix by reassigning logic to macrocells to retain pinout as designs change. The logic allocation scheme in the
MACH 5 device allows for the implementation of large equations (up to 32 product terms) with only one pass
through the logic array.
Table 4. Product Term Steering Options for PT Clusters and Macrocells
Macrocell
Available Clusters
Macrocell
Available Clusters
M0
C0, C1, C2, C3, C4
M8
C5, C6, C7, C8, C9, C10, C11, C12
M1
C0, C1, C2, C3, C4, C5
M9
C6, C7, C8, C9, C10, C11, C12, C13
M2
C0, C1, C2, C3, C4, C5, C6
M10
C7, C8, C9, C10, C11, C12, C13, C14
M3
C0, C1, C2, C3, C4, C5, C6, C7
M11
C8, C9, C10, C11, C12, C13, C14, C15
M4
C0, C1, C2, C3, C4, C5, C6, C7
M12
C8, C9, C10, C11, C12, C13, C14, C15
M5
C1, C2, C3, C4, C5, C6, C7, C8
M13
C9, C10, C11, C12, C13, C14, C15
M6
C2, C3, C4, C5, C6, C7, C8, C9
M14
C10, C11, C12, C13, C14, C15
M7
C3, C4, C5, C6, C7, C8, C9, C10
M15
C11, C12, C13, C14, C15
Block
Interconnect
Interconnect Feeder
Block
Feeder
32
I/Os
16
2
Macrocells
Logic
Alocator
Control Generator
OE Generator
Product-term
Array
32
Input Register
Path
2
Local
Feedback
20446G-002
Figure 2. PAL Block Structure
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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| M5LV-128/74-12VC | IC CPLD 128MC 74I/O 100TQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M5LV-256/104-10AC | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture |
| M5LV-256/104-10AI | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture |
| M5LV-256/104-10HC | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture |
| M5LV-256/104-10HI | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture |
| M5LV-256/104-10VC | 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAM HI DENSITY CPLD RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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