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参数资料
| 型号： | M5LV-128/74-15VI |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 42/42页 |
| 文件大小： | 0K |
| 描述： | IC CPLD 128MC 74I/O 100TQFP |
| 标准包装： | 90 |
| 系列： | MACH® 5 |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 15.0ns |
| 电压电源 - 内部： | 3 V ~ 3.6 V |
| 宏单元数： | 128 |
| 输入/输出数： | 74 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 托盘 |
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MACH 5 Family
9
MACH 5 TIMING MODEL
The primary focus of the MACH 5 timing model is to accurately represent the timing in a MACH 5 device,
and at the same time, be easy to understand. This model accurately describes all combinatorial and registered
paths through the device, making a distinction between
internal feedback and external feedback. A signal
uses internal feedback when it is fed back into the switch matrix or block without having to go through the
output buffer. The input register specifications are also reported as internal feedback. When a signal is fed back
into the switch matrix after having gone through the output buffer, it is using external feedback.
The parameter, tBUF, is defined as the time it takes to go through the output buffer to the I/O pad. If a signal
goes to the internal feedback rather than to the I/O pad, the parameter designator is followed by an “i”. By
adding tBUF to this internal parameter, the external parameter is derived. For example, tPD = tPDi + tBUF. A
diagram representing the modularized MACH 5 timing model is shown in Figure 7. Refer to the Technical
Note entitled MACH 5 Timing and High Speed Design for a more detailed discussion about the timing parameters.
INPUT REG/
INPUT LATCH
tSIR (S/A)
tHIR (S/A)
tSIL
tHIL
tSRR
tCES
tCEH
tCO (S/A) i
tPDILi
tGOAi
tSRi
tBLK
tSEG
CE
SR
(External Feedback)
(Internal Feedback)
Q
tS (S/A)
tH (S/A)
tSAL
tHAL
tSRR
tCES
tCEH
tPDi
tCO (S/A) i
tPDLi
tGOAi
tSRi
COMB/DFF/
LATCH
CE
SR
tPL1
tPL2
tPL3
IN
OUT
tPT
tEA
tER
tBUF
tSLW
PIN CLK
Q
20446G-014
Figure 7. MACH 5 Timing Model
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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| MAX5911ESA+ | IC HOT-SWAP SWITCH -48V 8-SOIC |
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| MIC2211-MPBML TR | IC REG LDO 2.8V/3V 10-MLF |
| M5LV-128/74-12VC | IC CPLD 128MC 74I/O 100TQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M5LV-256/104-10AC | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture |
| M5LV-256/104-10AI | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture |
| M5LV-256/104-10HC | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture |
| M5LV-256/104-10HI | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture |
| M5LV-256/104-10VC | 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAM HI DENSITY CPLD RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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