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参数资料
| 型号： | M5M5Y5672TG-25 |
| 厂商： | Mitsubishi Electric Corporation |
| 英文描述： | 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM |
| 中文描述： | 18874368位（262144 - Word的72位）网络的SRAM |
| 文件页数： | 11/27页 |
| 文件大小： | 240K |
| 代理商： | M5M5Y5672TG-25 |
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MITSUBISHI LSIs
M5M5Y5672TG – 25,22,20
18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
11
MITSUBISHI
ELECTRIC
Advanced Information
M5M5Y5672TG REV.0.1
In some applications it may be appropriate to pause between banks; to deselect both SRAMs with E1# before resuming read
operations. An E1# deselect at a bank switch will allow at least one clock to be issued from the new bank before the first read cycle
in the bank. Although the following drawing illustrates a E1# read pause upon switching from Bank 1 to Bank 2, a write to Bank 2
would have the same effect, causing the SRAM in Bank 2 to issue at least one clock before it is needed.
Output Driver Impedance Control
The ZQ pin of SRAMs supplied with selectable impedance drivers, allows selection between SRAM nominal drive strength
(ZQ low) for multi-drop bus applications and low drive strength (ZQ floating or high) point-to-point applications.
CLK
A
ADD
E1#
E2# Bank1
E2 Bank2
Q(A)
B
C
D
E
DQ
Bank1
CQ
Bank1
CQ Bank1
+ CQ Bank2
Q(B)
Q(C)
DQ
Bank2
CQ
Bank2
Pipelined Read Bank Switch with E1# Deselect
Note10. E1# does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously
deselected by E2 or E3 being sampled false.
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