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参数资料
| 型号： | M68AW512MN70ND1T |
| 厂商： | 意法半导体 |
| 英文描述： | 8 Mbit (512K x16) 3.0V Asynchronous SRAM |
| 中文描述： | 8兆位（为512k × 16）3.0V异步SRAM |
| 文件页数： | 15/19页 |
| 文件大小： | 296K |
| 代理商： | M68AW512MN70ND1T |
15/19
M68AW512M
Figure 13. Low V
CC
Data Retention AC Waveforms
Table 9. Low V
CC
Data Retention Characteristics
Symbol
Parameter
Note: 1. All other Inputs at V
IH
≥
V
CC
–0.2V or V
IL
≤
0.2V.
2. Tested initially and after any design or process changes that may affect these parameters. t
AVAV
is Read cycle time.
3. No input may exceed V
CC
+0.2V.
Test Condition
Min
Typ
Max
Unit
I
CCDR (1)
Supply Current (Data Retention)
V
CC
= 1.5V, E
≥
V
CC
–0.2V or
UB = LB
≥
V
CC
–0.2V, f = 0
(3)
5
10
μA
t
CDR (1,2)
Chip Deselected to Data
Retention Time
0
ns
t
R (2)
Operation Recovery Time
t
AVAV
ns
V
DR (1)
Supply Voltage (Data Retention)
E
≥
V
CC
–0.2V or
UB = LB
≥
V
CC
–0.2V, f = 0
1.5
V
AI05805
DATA RETENTION MODE
tR
3.6V
tCDR
VCC 2.7V
VDR > 1.5V
E or UB/LB
E
≥
VDR – 0.2V or UB = LB
≥
VDR – 0.2V
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