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| 型号： | M68HC16Y1CFC |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, MICROCONTROLLER, PQFP16 |
| 封装： | QFP-160 |
| 文件页数： | 133/138页 |
| 文件大小： | 784K |
| 代理商： | M68HC16Y1CFC |
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MOTOROLA
MC68HC16Y1
94
MC68HC16Y1TS/D
6.3 Digital Control Subsystem
The digital control section includes conversion sequence control logic, channel and reference select
logic, successive approximation register, eight result registers, a port data register, and control/status
registers. It controls the multiplexer and the output of the RC array during the sample and conversion
periods, stores the results of comparison in the successive-approximation register, then transfers the
result to a result register.
6.4 Bus Interface Subsystem
The bus interface contains logic necessary to interface the ADC to the intermodule bus. The ADC is
designed to act as a slave device on the bus. The interface must respond with appropriate bus cycle
termination signals and supply appropriate interface timing to the other submodules.
6.5 ADC Registers
The module configuration register is used to initialize the ADC.
STOP — STOP Mode
0 = Normal operation
1 = Low-power operation
STOP places the ADC in low-power state by disabling the ADC clock and powering down the analog
circuitry. Setting STOP will abort any conversion in progress. STOP is set to logic level one at reset,
and may be cleared to logic level zero by the CPU.
Clearing STOP enables normal ADC operation. However, because analog circuitry bias current has
been turned off, there is a period of recovery before output stabilization.
FRZ[1:0] — Freeze 1
The FRZ field is used to determine ADC response to assertion of the IFREEZE signal. The following
table shows possible responses.
SUPV — Supervisor/Unrestricted
0 = Unrestricted access
1 = Supervisor access
SUPV defines access to assignable ADC registers. Because the CPU16 in the MC68HC16Y1 operates
in supervisor mode only, this bit has no effect.
ADTEST — ADC Test Register
$YFF702
ADTEST is used with the SCIM test register for factory test of the ADC.
ADCMCR — Module Configuration Register
$YFF700
15
14
13
12
8
7
6
0
STOP
FRZ
NOT USED
SUPV
NOT USED
RESET:
1
0
1
FRZ
Response
00
Ignore IFREEZE
01
Reserved
10
Finish conversion, then freeze
11
Freeze immediately
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