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参数资料
| 型号： | M68LC302CAF16VCT |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100 |
| 文件页数： | 45/128页 |
| 文件大小： | 641K |
| 代理商： | M68LC302CAF16VCT |
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MC68EN302 Module Bus Controller
2-6
MC68EN302 REFERENCE MANUAL
MOTOROLA
2.7 PARITY CONTROL AND STATUS REGISTER (PCSR)
This register controls and gives the status of the parity checking portions of the parity
circuitry. This register is set to 0x0000 upon hardware reset.
PIE—Parity Error Interrupt Enable. This bit determines if an interrupt is generated when a
parity error is detected.
0 = No interrupt is generated.
1 = Either a level 3 or level 5 interrupt is generated, depending upon the encoding of
the MIL bit in the IER register.
OPAR—Odd Parity. This bit is used to determine if odd or even parity is used.
0 = Parity is even.
1 = Parity is odd.
PEC—Parity Error Chip Selects (PEC3–PEC0). These status bits indicate that there was a
parity error in the corresponding Chip Select Bank. If one of the three bits is set to one, a
parity error is detected in the corresponding bank. If the PIE bit is set, a level 5 (or 3) interrupt
is driven to the processor as long as one of the PEC3–PEC0 bits are set. PEC3–PEC0 are
sticky bits which are cleared when a one is written to them or upon hardware reset. Writing
a zero does not change the value of the PEC bits. The PARITYE pin is asserted until the
PEC3–PEC0 bits are all cleared.
NOTE
If the Parity Pin Enable bit (PPE in MBC CSR) = 0 and parity is
enabled with CSPE in CSER3–CSER0, then a parity error will be
reported on the associated PEC bit.
PED—Parity Error DRAM (PED1–PED0). These status bits indicate that there was a parity
error in the corresponding DRAM bank. If one of the two bits is set to one, a parity error is
detected in the corresponding bank. If the PIE bit is set, a level 5 (or 3) interrupt is driven to
the processor as long as one of the PED bits is set. PED are sticky bits which are cleared
when a one is written to them or upon hardware reset. Writing a zero does not change the
value of the PED bits. Writing a zero does not change the value of the PED bits. The
PARITYE pin is asserted as long as a PED bit is set.
NOTE
If the Parity Pin Enable bit (PPE in MBC CSR) = 0 and parity is
enabled on the DRAM interface (PE1 and/or PE0 = 1 in DCR)
then a parity error will be reported on PED1–PED0.
PIV—Parity Error Interrupt Vector (PIV7–PIV0). If the PIE bit is set, a parity error generates
a level 5 (or 3) interrupt. The PIV bits determine what interrupt vector is returned in response
to a level 5 (or 3) parity error interrupt.
15
14
13
12
11
10
9876543210
PIE
OPAR PEC3 PEC2 PEC1 PEC0 PED1 PED0
PIV7
PIV6
PIV5
PIV4
PIV3
PIV2
PIV1
PIV0
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相关代理商/技术参数 |
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| M68LC302CAF20VCT | 功能描述:微处理器 - MPU 68K INTGR COM PROC DMA RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
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| M68LC302CPU20VCT | 功能描述:IC MPU NETWORK 20MHZ 100-LQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:M683xx 标准包装:2 系列:MPC8xx 处理器类型:32-位 MPC8xx PowerQUICC 特点:- 速度:133MHz 电压:3.3V 安装类型:表面贴装 封装/外壳:357-BBGA 供应商设备封装:357-PBGA（25x25） 包装:托盘 |
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