参数资料
型号: M68LC302CAF16VCT
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封装: 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100
文件页数: 58/128页
文件大小: 641K
代理商: M68LC302CAF16VCT
MC68EN302 DRAM Control Module
3-4
MC68EN302 REFERENCE MANUAL
MOTOROLA
3.6.2 Read and Write Cycle Operation
Figure 3-1 shows two consecutive 4-clock accesses with a 2-clock precharge of RAS. RAS
is negated one clock before CAS to provide a longer precharge time between consecutive
hits in a given bank.
Figure 3-1. Consecutive Four-Clock Accesses
In some cases, a DRAM access is not possible in a 4-clock cycle. In still other cases, the
precharge time of 2 clocks is not enough for the given DRAM. Figure 3-2 shows two
consecutive 5-clock accesses, with a 3-clock RAS precharge. Note that the DRAM signals
are delayed in the second cycle with respect to the processor bus signals, allowing a longer
RAS precharge time.
S2
S3 S4 S5 S6
S1
CLOCK
S0
S7 S0 S1 S2 S3
ADDR
RAS
CAS
DRAMRW
DATA/
AS
UDS/LDS
S4 S5 S6 S7
AMUX
S0
PARITY
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