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参数资料
| 型号： | M68LC302CAF16VCT |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100 |
| 文件页数： | 86/128页 |
| 文件大小： | 641K |
| 代理商： | M68LC302CAF16VCT |
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ETHERNET Controller
MOTOROLA
MC68EN302 REFERENCE MANUAL
4-21
— Guarantees minimum inter-frame gap (IFG) of 9.6
sec between CarrierSense
deasserted and next frame transmitted.
— Provides 8 byte PA + SFD
— Appends 32 bit JAM sequence (all 1’s) and start backoff timer upon collision
— Appends 32 bit CRC (if TC = 1) or bad CRC if aborting frame
— Defers to CarrierSense for 6
sec, then ignores CarrierSense for 3.6 sec during
InterFrameGap
— Collision Retry occurs under the 802.3 truncated binary exponential backoff
algorithm
— Detects a babbling transmission and generates BABT interrupt
— Aborts Frame transmission if Transmit FIFO underflow, ETHER_EN deassertion
during frame transmission, Collision Retry Limit exceeded, Late Collision or
Collision and DRTY = 1
Provides Transmit Frame Status
— Generates the DEF, HB, LC, RL, RC, UN and CSL status fields written into the end
of frame transmit buffer descriptor which provide status on the transmission of the
frame. The definition of these fields is based on the Layer Management section of
the 802.3 standard. These fields are valid after the heartbeat window following the
successful transmission of a frame or if the collision retry limit (16 attempts) is
exceeded. A “XmitStatusReady” signal is asserted to the transmit buffer descriptor
control logic when this status is available
All logic in the Ethernet Transmit block runs synchronously with the Ethernet TCLK provided
by an external Ethernet physical layer component(s).
NOTE
Deasserting ETHER_EN during frame transmission is NOT
recommended as ETHER_EN is used as a reset signal in the
Ethernet controller logic. The recommended procedure is to
assert the GTS bit to gracefully halt transmission. Once the GRA
interrupt is received indicating that transmission has completed,
then deassert ETHER_EN.
4.5.2 ETHERNET RECEIVE
The receive block consists of the following submodules:
Serial to Parallel Conversion
Receive Protocol Control
— Controls data path by stripping PA, SFD, and dribble bits
— Detects runt frames, and signals REJECT to the receive FIFO
— Detects giant frames, generates the BABR interrupt and discards the rest of frame
— Provides count to determine frame length (in bytes)
— Provides for interframe recovery if a minimum receive interframe gap of
approximately 2.4
sec is provided.
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相关代理商/技术参数 |
参数描述 |
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| M68LC302CAF20VCT | 功能描述:微处理器 - MPU 68K INTGR COM PROC DMA RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| M68LC302CPU16VCT | 功能描述:IC MPU NETWORK 16MHZ 100-LQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:M683xx 标准包装:2 系列:MPC8xx 处理器类型:32-位 MPC8xx PowerQUICC 特点:- 速度:133MHz 电压:3.3V 安装类型:表面贴装 封装/外壳:357-BBGA 供应商设备封装:357-PBGA（25x25） 包装:托盘 |
| M68LC302CPU20VCT | 功能描述:IC MPU NETWORK 20MHZ 100-LQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:M683xx 标准包装:2 系列:MPC8xx 处理器类型:32-位 MPC8xx PowerQUICC 特点:- 速度:133MHz 电压:3.3V 安装类型:表面贴装 封装/外壳:357-BBGA 供应商设备封装:357-PBGA（25x25） 包装:托盘 |
| M68LGL061X | 制造商:Panasonic Industrial Company 功能描述:SUB ONLY CRT |
| M68LGL061XA | 制造商:Panasonic Industrial Company 功能描述:CRT OR M68LGL061X |
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