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参数资料
| 型号： | M7010R |
| 厂商： | 意法半导体 |
| 英文描述： | 16K x 68-bit Entry NETWORK SEARCH ENGINE |
| 中文描述： | 16K的× 68位进入网络搜索引擎 |
| 文件页数： | 48/67页 |
| 文件大小： | 449K |
| 代理商： | M7010R |
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M7010R
48/67
LRAM and LDEV Description
When search engines are cascaded using multiple
M7010R devices, the SADR, CE_L, and WE_L
(tri-state signals) are all tied together. To eliminate
external pull-up and pull-downs, one device in a
bank is designated as the default driver. For non-
SEARCH or non-LEARN cycles (see LEARN
COMMAND, page 48) or SEARCH cycles with a
global miss, the SADR, CE_L, and WE_L signals
are driven by the device with the LRAM Bit set. It
is important that only one device in a bank of cas-
caded search engines have this bit set. Failure to
do so will cause contention on SADR, CE_L, and
WE_L, and can potentially cause damage to the
device(s).
Similarly, when search engines using multiple
M7010R devices are cascaded, SSF and SSV (al-
so tri-state signals) are tied together. To eliminate
external pull-up and pull-downs, one device in a
bank is designated as the default driver. For non-
SEARCH or SEARCH cycles with a global miss,
the SSF and SSV signals are driven by the device
with the LRAM Bit set. It is important that only one
device in a bank of cascaded search engines have
this bit set. Failure to do so will cause contention
on SSF and SSV, and can potentially cause dam-
age to the device(s).
LEARN COMMAND
Bit [0] of each 68-bit data location specifies wheth-
er an entry in the database is occupied. If all the
entries in a device are occupied, the device as-
serts FULO signal to inform the downstream de-
vices that it is full.
The result of this communication between depth-
cascaded devices determines the global FULL
signal for the entire table. On a miss by the
SEARCH (signalled to the ASIC through the SSV
and SSF signals [SSV = 1, SSF = 0]), the host
ASIC can apply the LEARN command to learn the
entry from a comparand register to the next-free
location (see The NFA Register, page 24). The
NFA updates to the next-free location following
each WRITE or LEARN command.
In a depth-cascaded table, only a single device will
learn the entry through the application of a LEARN
Instruction. The determination of the LEARN de-
vice is based on the FULI and FULO signalling be-
tween the devices. The first non-full device learns
the entry by storing the contents of the specified
comparand registers to the location(s) pointed to
by the NFA.
In a x68-configured table, the LEARN command
writes a single 68-bit location. In a 136-bit-config-
ured table, the LEARN command writes the next
even and odd 68-bit locations. In 136-bit mode,
Bit[0] of the even and odd 68-bit locations is '0,' in-
dicating that they are cascaded empty, or '1,'
which indicates that they are occupied.
The global FULL signal indicates to the table con-
troller (the host ASIC) that all entries within a block
are occupied and that no more entries can be
learned. The M7010R device updates the signal to
a data array after each WRITE or LEARN com-
mand. Also using the NFA Register as part of the
SRAM address, the LEARN command generates
a WRITE cycle to the external SRAM.
The LEARN command is supported on a single
block containing up to eight devices if the table is
configured as either a x68 or a x136. The LEARN
command is not supported for x272-configured ta-
bles.
The LEARN operation lasts two CLK cycles. The
sequence of this operation is as follows:
–
Cycle 1A:
The host ASIC applies the LEARN
Instruction on CMD[1:0] using CMDV = 1. The
CMD[5:2] field specifies the index of the com-
parand register pair that will be written to the
data array in the 136-bit-configured table. For a
LEARN in a 68-bit-configured table, the even-
numbered comparand specified by this index
will be written. CMD[8:6] carries the bits that will
be driven on SADR[21:19] in the SRAM WRITE
cycle.
–
Cycle 1B:
The host ASIC continues to drive
CMDV to '1,' CMD[1:0] to '11,' and CMD[5:2]
with the comparand pair index. CMD[6] must be
set to '0' if the LEARN is being performed on a
68-bit-configured table, and to '1' if the LEARN
is being performed on a 136-bit-configured ta-
ble.
–
Cycle 2:
The host ASIC drives CMDV to '0.'
At the end of Cycle 2, a new instruction can begin.
SRAM WRITE latency is the same as the
SEARCH to the SRAM READ cycle measured
from the second cycle of the LEARN Instruction.
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