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| 型号： | MA31753 |
| 厂商： | Dynex Semiconductor Ltd. |
| 英文描述： | DMA Controller (DMAC) For An MA31750 System |
| 中文描述： | DMA控制器（DMAC）对于MA31750系统 |
| 文件页数： | 10/30页 |
| 文件大小： | 243K |
| 代理商： | MA31753 |
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MA31753
10/30
5.4 AREA 1 AND 2 PB, PS AND AS
These readable and writable registers store the Page Bank, Processor and Address State information to be used when
accessing areas 1 and 2. When areas are defined within IO space, PB, PS and AS are set to zero.
5.5 TRANSFER INTERVAL
This readable and writable register gives the number of CLK cycles between each DMA request generated during area to
area transfers. The number entered as the interval value corresponds to a clock cycle interval increasing by 32 as follows:
0
1
2
3
4
..
14
15
=>
=>
=>
=>
=>
..
=>
=>
- (externally triggered DMA requests)
0 (continuous DMA requests until the block is completed.
32
64
96
..
416
448
This function is valid only for transfers on channels 0 and 1. Channels 2 and 3 work ony only on externally triggered requests.
5.6 CONFIGURATION WORD
The DMA controller snoops the system address bus for the XIO address 0x8410. When this appears, the DMA stores the data
bus (qualified by DSN low) in an internal copy of the CPU configuration word.
OIN
PB0
PS0
AS0
PB3
PS3
AS3
D0
D15
Interval
D0
D15
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