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参数资料
| 型号： | MA31753 |
| 厂商： | Dynex Semiconductor Ltd. |
| 英文描述： | DMA Controller (DMAC) For An MA31750 System |
| 中文描述： | DMA控制器（DMAC）对于MA31750系统 |
| 文件页数： | 6/30页 |
| 文件大小： | 243K |
| 代理商： | MA31753 |
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MA31753
6/30
4.0 DETAILED REGISTER DESCRIPTION
The internal registers on the DMA controller can be located
in either memory or IO addressing space. 32 words are control
registers and 480 words are the DMA instruction registers.
The address lines A[7:15] are used to decode the registers.
(A[0:6] are decoded to generate CSN low ie. the user can
place the DMA on the address map.)
4.1 MODE REGISTERS
CA
read 0: channel not active
write 0: stop channel
read 1: channel active
write 1: start channel
This bit will be set low at an error or EOT condition
Mode 000:
Single Word
Double Word
Burst Mode
Not used (channel not started)
Area to Area, Memory to Memory
Area to Area, Memory to IO
Area to Area, IO to Memory
Area to Area, IO to IO
001:
010:
011:
100:
101:
110:
111:
A1M
Area 1 Mode
For single, double and burst modes
00:
Read from memory, incrementing address
01:
Read from memory, decrementing address
10:
Write to memory, incrementing address
11:
Write to memory, decrementing address
Area to area mode
00:
Area 1 address constant
01:
Area 1 address incrementing
10:
Area 1 address decrementing
11:
Area 1 address constant
A2M
Area 2 Mode (only used in area to area mode)
00:
Area 2 address constant
01:
Area 2 address incrementing
10:
Area 2 address decrementing
11:
Area 2 address constant
SEOT 0:
Signal ‘End of Transfer’ at end of current block
only of C=0
Always signal ‘End of Transfer’ at end of
current block.
1:
C
read 0: Perform no chaining
read 1: Perform chaining using the value of “next
Instruction” field as pointer
write 0: Perform no chaining even if defined by current
DMA instruction
write 1: Perform chaining as defined by current
instruction
Next
Inst
These 6 bits point to one of the 60 DMA instructions ie.
the next instruction to be executed.
If the number is 3C, 3D, 3E or 3F, then the transfer will
stop with the current block (ie. no chaining)
A[7:15]
0
.
.
1DF
1E0
1E1
1E2
1E3
1E4
1E5
1E6
1E7
1E8
1E9
1EA
1EB
1EC
1ED
1EE
1EF
1F0
1F1
1F2
1F3
1F4
1F5
1F6
1F7
1F8
1F9
1FA
1FB
1FC
1FD
1FE
1FF
Register Content
DMA Instruction
.
.
DMA Instruction
Channel 0 Mode
Channel 0 Remaining words
Channel 0 Area 1 current address
Channel 0 Area 1 current PB/AS/PS
Channel 0 Area 2 current address
Channel 0 Area 2 current PB/AS/PS
Channel 0 Status
DMA Mode / Status 1
Channel 1 Mode
Channel 1 Remaining words
Channel 1 Area 1 current address
Channel 1 Area 1 current PB/AS/PS
Channel 1 Area 2 current address
Channel 1 Area 2 current PB/AS/PS
Channel 1 Status
RESERVED
Channel 2 Mode
Channel 2 Remaining words
Channel 2 Area 1 current address
Channel 2 Area 1 current PB/AS/PS
Channel 2 Area 2 current address
Channel 2 Area 2 current PB/AS/PS
Channel 2 Status
RESERVED
Channel 3 Mode
Channel 3 Remaining words
Channel 3 Area 1 current address
Channel 3 Area 1 current PB/AS/PS
Channel 3 Area 2 current address
Channel 3 Area 2 current PB/AS/PS
Channel 3 Status
RESERVED
Parity
Yes
.
.
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Mode Register
CA
Mode
A1M
A2M
SEOT C
Next Instruction
D0
D15
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