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参数资料
| 型号： | MACH111SP-5VC |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | High-Performance EE CMOS Programmable Logic |
| 中文描述： | EE PLD, 5 ns, PQFP44 |
| 封装： | TQFP-44 |
| 文件页数： | 34/48页 |
| 文件大小： | 1136K |
| 代理商： | MACH111SP-5VC |
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4
MACH 1 & 2 Families
FUNCTIONAL DESCRIPTION
Each MACH 1 and 2 device consists of multiple, optimized PAL blocks interconnected by a switch
matrix. The switch matrix allows communication between PAL blocks, and routes inputs to the PAL
blocks. Together, the PAL blocks and switch matrix allow the logic designer to create large designs
in a single device instead of using multiple devices.
The switch matrix takes all dedicated inputs and signals from the input switch matrices and routes
them as needed to the PAL blocks. Feedback signals that return to the same PAL block still must
go through the switch matrix. This mechanism ensures that PAL blocks in MACH devices
communicate with each other with guaranteed xed timing (SpeedLocking).
The switch matrix makes a MACH device more advanced than simply several PAL devices on a
single chip. It allows the designer to think of the device not as a collection of blocks, but as a
single programmable device; the software partitions the design into PAL blocks through the
central switch matrix so that the designer does not have to be concerned with the internal
architecture of the device.
14051K-002
Figure 1. Overall Architecture of MACH 1 & 2 Devices
Array and
Allocator
Output
Macrocells
Buried
Macrocells
I/O Cells
Buried Macrocell Feedback
Output Macrocell Feedback
I/O Pin Feedback
I/O Pins
Switch
Matrix
PAL Block
I/O Pins
PAL Block
Clock/Input Pins
Dedicated Input
Note:
1. There are no buried macrocells in MACH 1 devices. All macrocells are output macrocells.
PAL Block
Device
PAL Blocks
Macrocells per Block
I/Os per Block
Product Terms per Block
MACH111(SP)
21616
70
MACH131(SP)
41616
70
MACH211(SP)
416
8
68
MACH221(SP)
812
6
52
MACH231(SP)
816
8
68
(note 1)
I/O Pins
相关PDF资料 |
PDF描述 |
|---|---|
| MACH111SP-7JC | High-Performance EE CMOS Programmable Logic |
| MACH111SP-7JI | High-Performance EE CMOS Programmable Logic |
| MACH111SP-7VC | High-Performance EE CMOS Programmable Logic |
| MACH131SP-12YI | High-Performance EE CMOS Programmable Logic |
| MACH131SP-14YI | High-Performance EE CMOS Programmable Logic |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MACH111SP-7JC | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:High-Performance EE CMOS Programmable Logic |
| MACH111SP-7JI | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:High-Performance EE CMOS Programmable Logic |
| MACH111SP-7VC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MACH11SP | 制造商:未知厂家 制造商全称:未知厂家 功能描述:High-Performance EE CMOS In-System Programmable Logic |
| MACH120-12 | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:High-Performance EE CMOS Programmable Logic |
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