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| 型号： | MAX11040GUU+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 21/35页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT 4CH 38-TSSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 位数： | 24 |
| 采样率（每秒）： | 64k |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 4 |
| 功率耗散（最大）： | 108mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-TFSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 38-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 4 个差分，双极 |
| 配用： | MAXSPCSPARTAN6+-ND - ADC and DAC Eval Expansion Board |
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MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
28
Maxim Integrated
S
SY
YN
NC
C for Simultaneous
Sampling with Multiple Devices
The SYNC input permits multiple devices to sample
simultaneously. The mismatch between the power-up
reset of multiple devices causes the devices to begin
conversion at different times. After a falling edge on the
SYNC input, the device completes the current conver-
sion and then synchronizes subsequent conversions
(see Figure 16).
Upon a SYNC falling edge, the devices measure the time
between the SYNC falling edge to the preceding DRDY-
OUT falling edge, wait until the next DRDYOUT falling
edge, then pause the ADC for the measured amount of
time. Figure 16 shows an example where the converter
is regularly sampling the input and producing a DRDY-
OUT with a period tS. The effect of a SYNC falling edge
as shown in Figure 16 is described in sequence below:
1) A SYNC falling edge is issued two XIN clock cycles
after the DRDYOUT event 2.
2) The converter remembers the two XIN clock cycles,
and completes the current sample, issuing DRDYOUT
event 3 a period of tS after DRDYOUT event 2.
3) Then, the converter pauses for the remembered time
period, two XIN clock cycles for this example.
4) Correspondingly, DRDYOUT event 4 is issued two
XIN cycles later than it would have without the
SYNC falling edge.
5) The process continues as normal with DRDYOUT
event 5 appearing tS after DRDYOUT event 4.
XIN
NOTE: THE LATENCY IS NOT TO SCALE.
DRDYOUT
SYNC
AIN_
MEASURE
PAUSE
DELAY 2
CYCLES
tS
1
2
3
4
5
6
Figure 16. Effect of a SYNC Falling Edge
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX11040K | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs |
| MAX11040K_1111 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs |
| MAX11040K_12 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:MAX11040K Evaluation Kit/Daughterboard |
| MAX11040KDBEVKIT | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:MAX11040K Evaluation Kit/Daughterboard |
| MAX11040KDBEVKIT# | 功能描述:数据转换 IC 开发工具 MAX5135/11040/11612 Eval Kit w/ FMC RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
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