参数资料
型号: MAX11040GUU+T
厂商: Maxim Integrated Products
文件页数: 31/35页
文件大小: 0K
描述: IC ADC 24BIT 4CH 38-TSSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
位数: 24
采样率(每秒): 64k
数据接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 4
功率耗散(最大): 108mW
电压电源: 模拟和数字
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 38-TFSOP(0.173",4.40mm 宽)
供应商设备封装: 38-TSSOP
包装: 带卷 (TR)
输入数目和类型: 4 个差分,双极
配用: MAXSPCSPARTAN6+-ND - ADC and DAC Eval Expansion Board
MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
5
Maxim Integrated
Note 1: Devices are production tested at +105°C. Specifications to -40°C are guaranteed by design.
Note 2: Tested at VAVDD = VDVDD = +3.0V.
Note 3: Integral nonlinearity is the deviation of the analog value at any code from its ideal value after the offset and gain errors are
removed.
Note 4: Offset nulled.
Note 5: Offset and gain drift defined as change in offset and gain error vs. full scale.
Note 6: Noise measured with AIN_+ = AIN_- = AGND.
Note 7: Relative accuracy is defined as the difference between the actual RMS amplitude and the ideal RMS amplitude of a 62.5Hz
sine wave, measured over one cycle at a 16ksps data rate, expressed as a fraction of the ideal RMS amplitude. The rela-
tive accuracy specification refers to the maximum error expected over 1 million measurements. Calculated from SNR. Not
production tested.
Note 8: Latency is a function of the sampling rate and XIN clock.
Note 9: Voltage levels below the positive fault threshold and above the negative fault threshold, relative to AGND on each individ-
ual AIN_+ and AIN_- input, do not trigger the analog input protection circuitry.
Note 10: Test performed using RXD MP35.
Note 11: All digital inputs at DGND or DVDD.
Note 12: SYNC is captured by the subsequent XIN clock if this specification is violated.
Note 13: Delay from DVDD exceeds 2.0V until digital interface is operational.
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +3.0V to +3.6V, VDVDD = +2.7V to VAVDD, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = +2.5V (external), CREFIO =
CREF0 = CREF1 = CREF2 = CREF3 = 1μF to AGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLOAD = 30pF
1.5
10
16
SCLK Rise to DOUT Valid
tDOT
CLOAD = 100pF
< 16
ns
CS Fall to DOUT Enable
tDOE
CLOAD = 30pF
0.3
20
ns
CS Rise to DOUT Disable
tDOD
CLOAD = 30pF
0.7
16
ns
CS Pulse Width
tCSW
16
ns
CASCIN-to-SCLK Rise Setup
tSC
16
ns
SCLK Rise to CASCOUT Valid
tCOT
CLOAD = 100pF
20
ns
SYNC Pulse Width
tSYN
2
XIN
Clock
Cycles
XIN Clock Pulse Width
tXPW
16
ns
DRDYIN to DRDYOUT
tDRDY
CLOAD = 30pF
20
ns
XIN Clock to DRDYOUT Delay
tXDRDY
DRDYIN = DGND
40
ns
XIN Clock Period
tXP
40
ns
XIN Clock to SYNC Setup
tSS
(Note 12)
16
ns
SYNC to XIN Clock Hold
tHS
(Note 12)
5
ns
XIN-to-CLKOUT Delay
tXCD
40
ns
Power-On Reset Delay
(Note 13)
< 1
ms
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