参数资料
型号: MAX1300BEUG+T
厂商: Maxim Integrated Products
文件页数: 6/31页
文件大小: 0K
描述: IC ADC 16BIT SPI/SRL 24TSSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
位数: 16
采样率(每秒): 115k
数据接口: MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 976mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 24-TSSOP
包装: 带卷 (TR)
输入数目和类型: 8 个单端,单极;8 个单端,双极;4 个差分,双极
MAX1300/MAX1301
Power Supplies
To maintain a low-noise environment, the MAX1300 and
MAX1301 provide separate power supplies for each
section of circuitry. Table 1 shows the four separate
power supplies. Achieve optimal performance using
separate AVDD1, AVDD2, DVDD, and DVDDO sup-
plies. Alternatively, connect AVDD1, AVDD2, and
DVDD together as close to the device as possible for a
convenient power connection. Connect AGND1,
AGND2, AGND3, DGND, and DGNDO together as
close to the device as possible. Bypass each supply to
the corresponding ground using a 0.1F capacitor
(Table 1). If significant low-frequency noise is present,
add a 10F capacitor in parallel with the 0.1F bypass
capacitor.
Converter Operation
The MAX1300/MAX1301 ADCs feature a fully differen-
tial, successive-approximation register (SAR) conver-
sion technique and an on-chip T/H block to convert
voltage signals into a 16-bit digital result. Both single-
ended and differential configurations are supported
with programmable unipolar and bipolar signal ranges.
Track-and-Hold Circuitry
The MAX1300/MAX1301 feature a switched-capacitor
T/H architecture that allows the analog input signal to be
stored as charge on sampling capacitors. See Figures 2,
3, and 4 for T/H timing and the sampling instants for
each operating mode. The MAX1300/MAX1301 analog
input circuitry buffers the input signal from the sampling
capacitors, resulting in a constant input impedance with
varying input voltage (Figure 5).
Analog Input Circuitry
Select differential or single-ended conversions using the
associated analog input configuration byte (Table 2).
The analog input signal source must be capable of dri-
ving the ADC’s 17k
input resistance (Figure 6).
Figure 6 shows the simplified analog input circuit. The
analog inputs are ±16.5V fault tolerant and are protected
by back-to-back diodes. The summing junction voltage,
VSJ, is a function of the channel’s input common-
mode voltage:
As a result, the analog input impedance is relatively con-
stant over input voltage as shown in Figure 5.
V
R
RR
V
R
RR
V
SJ
CM
.
=
+
×+
+
×
1
12
2 375
1
12
8- and 4-Channel, ±3 x VREF Multirange Inputs,
Serial 16-Bit ADCs
14
______________________________________________________________________________________
Table 1. MAX1300/MAX1301 Power Supplies and Bypassing
POWER
SUPPLY/GROUND
SUPPLY VOLTAGE
RANGE (V)
TYPICAL SUPPLY
CURRENT (mA)
CIRCUIT SECTION
BYPASSING
DVDDO/DGNDO
2.7 to 5.25
0.03
Digital I/O
0.1F to DGNDO
AVDD2/AGND2
4.75 to 5.25
135
Analog Circuitry
0.1F to AGND2
AVDD1/AGND1
4.75 to 5.25
3.0
Analog Circuitry
0.1F to AGND1
DVDD/DGND
4.75 to 5.25
0.8
Digital Control Logic and Memory
0.1F to DGND
Table 2. Analog Input Configuration Byte
BIT
NUMBER
NAME
DESCRIPTION
7
START
Start Bit. The first logic 1 after CS goes low defines the beginning of the analog input configuration byte.
6C2
5C1
4C0
Channel-Select Bits. SEL[2:0] select the analog input channel to be configured (Tables 4 and 5).
3
DIF/SGL
Differential or Single-Ended Configuration Bit. DIF/SGL = 0 configures the selected analog input channel
for single-ended operation. DIF/SGL = 1 configures the channel for differential operation. In single-ended
mode, input voltages are measured between the selected input channel and AGND1, as shown in
Table 4. In differential mode, the input voltages are measured between two input channels, as shown in
Table 5. Be aware that changing DIF/SGL adjusts the FSR, as shown in Table 6.
2R2
1R1
0R0
Input-Range-Select Bits. R[2:0] select the input voltage range, as shown in Table 6 and Figure 7.
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