参数资料
型号: MAX1300BEUG+T
厂商: Maxim Integrated Products
文件页数: 7/31页
文件大小: 0K
描述: IC ADC 16BIT SPI/SRL 24TSSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
位数: 16
采样率(每秒): 115k
数据接口: MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 976mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 24-TSSOP
包装: 带卷 (TR)
输入数目和类型: 8 个单端,单极;8 个单端,双极;4 个差分,双极
Single-ended conversions are internally referenced to
AGND1 (Tables 3 and 4). In differential mode, IN+ and
IN- are selected according to Tables 3 and 5. When
configuring differential channels, the differential pair fol-
lows the analog configuration byte for the positive
channel. For example, to configure CH2 and CH3 for a
±3 x VREF differential conversion, set the CH2 analog
configuration byte for a differential conversion with the
±3 x VREF range (1010 1100). To initiate a conversion
for the CH2 and CH3 differential pair, issue the com-
mand 1010 0000.
Analog Input Bandwidth
The MAX1300/MAX1301 input-tracking circuitry has a
2MHz small-signal bandwidth. The 2MHz input band-
width makes it possible to digitize high-speed transient
events. Harmonic distortion increases when digitizing
signal frequencies above 15kHz as shown in the THD
and -SFDR vs. Input Frequency plot in the
Typical
Operating Characteristics.
Analog Input Range and Fault Tolerance
Figure 7 illustrates the software-selectable single-ended
analog input voltage range that produces a valid digital
output. Each analog input channel can be independently
programmed to one of seven single-ended input ranges
by setting the R[2:0] control bits with DIF/SGL = 0.
MAX1300/MAX1301
8- and 4-Channel, ±3 x VREF Multirange Inputs,
Serial 16-Bit ADCs
______________________________________________________________________________________
15
CS
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DIN
S
C2
C1
C0
0
ANALOG INPUT
TRACK AND HOLD*
DOUT
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
BYTE 1
BYTE 2
BYTE 3
BYTE 4
SSTRB
HOLD
TRACK
HOLD
tACQ
HIGH
IMPEDANCE
HIGH
IMPEDANCE
*TRACK AND HOLD TIMING IS CONTROLLED BY SCLK.
fSAMPLE
≈ fSCLK / 32
SAMPLING INSTANT
Figure 2. External Clock-Mode Conversion (Mode 0)
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