参数资料
型号: MAX1368ECM+T
厂商: Maxim Integrated
文件页数: 24/36页
文件大小: 0K
描述: IC PANEL METER 3.5 DIG 48LQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,000
显示器类型: LED
配置: 7 段显示
接口: 串行
数字或字符: A/D,3.5 位数字
电源电压: 2.7 V ~ 5.25 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-LQFP(7x7)
包装: 带卷 (TR)
Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
Control and Status Registers
Command Byte (Write Only)
MSB
LSB
Bit 7
START(1)
Bit 6
R/ W
Bit 5
RS4
Bit 4
RS3
Bit 3
RS2
Bit 2
RS1
Bit 1
RS0
Bit 0
X
START: Start bit. The first 1 clocked into the MAX1366/
MAX1368 is the first bit of the command byte.
(R/ W ): Read/ Write . Set this bit to 1 to read from the
specified register. Set this bit to zero to write to the
selected register. Note that certain registers are read
Status Register (Read Only)
MSB
only. Write commands to a read-only register are
ignored.
(RS4–RS0): Register address bits. RS4 to RS0 specify
which register is accessed.
X: Don’t care.
LSB
SIGN
OVER
UNDER
LOW_BATT
DRDY
0
0
0
Default values: 00h
This register contains the status of the conversion
results.
SIGN: Latched negative-polarity indicator. Latches high
when the result is negative. Clears by reading the sta-
tus register, unless the condition remains true.
OVER: Overrange bit. Latches high if an overrange
condition occurs (the ADC result is larger than the
value in the overrange register). Clears by reading the
status register, unless the condition remains true.
UNDER: Underrange bit. Latches high if an underrange
condition occurs (the ADC result is less than the
Control Register (Read/Write)
MSB
value in the underrange register). Clears by reading the
status register, unless the condition remains true.
LOW_BATT: Low-battery bit. Latches high if the volt-
age at the LOWBATT is lower than 2.048V (typ). Clears
by reading the status register, unless the condition
remains true.
DRDY: Data-ready bit. Latches high to indicate a com-
pleted conversion result with valid data. Read the ADC
result register to clear this bit.
Bit 15
SPI/ ADC
Bit 14
EXTCLK
Bit 13
INTREF
Bit 12
DPON
Bit 11
DPSET2
Bit 10
DPSET1
Bit 9
PD_DIG
Bit 8
PD_ANA
LSB
Bit 7
HOLD
Bit 6
PEAK
Bit 5
RANGE
Bit 4
CLR
Bit 3
SEG_SEL
Bit 2
OFFSET_CAL1
Bit 1
OFFSET_
CAL2
Bit 0
ENABLE
Default values: 0000h
This register is the primary control register for the
MAX1366/MAX1368. It is a 16-bit read/write register. It
is used to indicate the desired clock and reference
source. It sets the LED display controls, range modes,
power-down modes, offset calibration, and the reset
register function (CLR).
ENABLE: (Default = 1.) LED driver enable bit. When set
to 1, the MAX1366/MAX1368 enables the LED display
drivers. A 0 in this location disables the LED dis-
play drivers.
OFFSET_CAL2: (Default = 0.) Enhanced offset-calibra-
tion start bit (RANGE = 1). To achieve the lowest possi-
ble offset in the ± 200mV input range, perform an
enhanced offset calibration by setting this bit to 1. The
calibration takes about nine cycles (1800ms). After the
calibration completes, set this bit to zero to resume
ADC conversions.
24
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