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参数资料
| 型号： | MAX1368ECM+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 6/36页 |
| 文件大小： | 0K |
| 描述： | IC PANEL METER 3.5 DIG 48LQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,000 |
| 显示器类型： | LED |
| 配置： | 7 段显示 |
| 接口： | 串行 |
| 数字或字符： | A/D，3.5 位数字 |
| 电源电压： | 2.7 V ~ 5.25 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 带卷 (TR) |
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Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
ELECTRICAL CHARACTERISTICS (continued)
(AV DD = DV DD = DAC_VDD = +2.7V to +5.25V, GND = 0, LEDG = 0, V LEDV = +2.7V to +5.25V, V REF+ - V REF- = 2.048V (external
reference), V EXT = 7V, V REG_AMP = +5.0V, C REF+ = 0.1μF, REF- = GND, C NEGV = 0.1μF. Internal clock mode, unless otherwise
noted. All specifications are at T A = T MIN to T MAX . Typical values are at T A = +25°C, unless otherwise noted.)
PARAMETER
CS Rise to DOUT Disable
CS Fall to DOUT Enable
SYMBOL
t TR
t DV
CONDITIONS
C LOAD = 50pF, Figures 11, 12
C LOAD = 50pF, Figures 11, 12
MIN
TYP
MAX
120
120
UNITS
ns
ns
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Integral nonlinearity is the deviation of the analog value at any code from its theoretical value after nulling the gain error
and offset error.
Offset calibrated. See OFFSET_CAL1 AND OFFSET_CAL2 in the On-Chips Registers section.
Offset nulled.
Offset-drift error is eliminated by recalibration at the new temperature.
The input voltage range for the analog inputs is given with respect to the voltage on the negative input of the differential pair.
V AIN+ or V AIN- = -2.2V to +2.2V. V REF+ or V REF- = -2.2V to +2.2V. All input structures are identical. Production tested on
AIN+ and REF+ only. V REF+ must always be greater than V REF- .
Measured at DC by changing the power-supply voltage from 2.7V to 5.25V and measuring the effect on the conversion
error with external reference. PSRR at 50Hz and 60Hz exceeds 120dB with filter notches at 50Hz and 60Hz ( Figure 1).
CLK and SCLK are disabled.
LED drivers are disabled.
Note 10: Power-supply currents are measured with all digital inputs at either GND or DV DD and with the device in internal clock mode.
Note 11: All input signals are specified with t RISE = t FALL = 5ns (10% to 90% of DV DD ) and are timed from a voltage level of 50% of
DV DD , unless otherwise noted.
Note 12: See the serial-interface timing diagrams (Figures 7–11).
Typical Operating Characteristics
(A VDD = D VDD = +5V, V DAC_VDD = +5.0V, GND = 0, LEDG = 0, V LEDV = +2.7V to +5.25V, V REF+ - V REF- = 2.048V (external reference),
V EXT = 7V, C REF+ = 0.1μF, REF- = GND, C NEGV = 0.1μF, RANGE bit = 1, internal clock mode. T A = +25°C, unless otherwise noted.)
SUPPLY CURRENT
MAX1366
1000
900
800
vs. SUPPLY VOLTAGE
700
600
SUPPLY CURRENT vs. TEMPERATURE
0.19
0.14
OFFSET ERROR vs. SUPPLY VOLTAGE
700
600
500
400
300
AV DD
DV DD
500
400
300
200
AV DD
DV DD
0.09
0.04
-0.01
-0.06
200
100
0
DAC_VDD
100
0
DAC_VDD
-0.11
-0.16
2.7
3.2
3.7
4.2
4.7
5.2
-40
-15
10
35
60
85
2.75
3.25
3.75
4.25
4.75
5.25
SUPPLY VOLTAGE (V)
TEMPERATURE ( ° C)
SUPPLY VOLTAGE (V)
6
_______________________________________________________________________________________
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