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参数资料
| 型号： | MAX1421CCM+D |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 3/17页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 40MSPS 48LQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 250 |
| 位数： | 12 |
| 采样率（每秒）： | 40M |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 214mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 托盘 |
| 输入数目和类型： | 1 个差分，双极 |
MAX1421
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
______________________________________________________________________________________
11
The MAX1421 provides three modes of reference oper-
ation:
Internal reference mode
Buffered external reference mode
Unbuffered external reference mode
In internal reference mode, the on-chip +2.048V
bandgap reference is active and REFIN, REFP, CML,
and REFN are left floating. For stability purposes,
bypass REFIN, REFP, REFN, and CML with a capacitor
network of 0.22F, in parallel with a 1nF capacitor to
AGND.
In buffered external reference mode, the reference volt-
age levels can be adjusted externally by applying a
stable and accurate voltage at REFIN.
In unbuffered external reference mode, REFIN is con-
nected to AGND, which deactivates the on-chip buffers
of REFP, CML, and REFN. With their buffers shut down,
these nodes become high impedance and can be dri-
ven by external reference sources, as shown in Figure 3.
Clock Inputs (CLK,
C
CL
LK
K)
The MAX1421’s CLK and CLK inputs accept both sin-
gle-ended and differential input operation, and accept
CMOS-compatible clock signals. If CLK is driven with a
single-ended clock signal, bypass CLK with a 0.1F
capacitor to AGND. Since the interstage conversion of
the device depends on the repeatability of the rising
and falling edges of the external clock, use a clock with
low jitter and fast rise and fall times (< 2ns). In particu-
lar, sampling occurs on the rising edge of the clock sig-
nal, requiring this edge to have the lowest possible
jitter. Any significant aperture jitter limits the SNR per-
formance of the ADC according to the following rela-
tionship:
where fIN represents the analog input frequency and
tAJ is the aperture jitter.
Clock jitter is especially critical for high input frequency
applications. The clock input should always be consid-
ered as an analog input and routed away from any ana-
log or digital signal lines.
The MAX1421 clock input operates with a voltage
threshold set to AVDD / 2. Clock inputs must meet the
specifications for high and low periods, as stated in the
Electrical Characteristics.
S
1
2t
dB
IN
AJ
NR
=×
××
20
10
log
π
MAX1421
REFIN
REFN
R
50
R
+1V
R
50
50
R
AVDD
CML
1nF
0.22
F
1nF
0.22
F
1nF
0.22
F
AGND
AVDD
2
AVDD
4
MAX4284
( )
REFP
+ 1V
(
)
AVDD
2
+ 1V
(
)
AVDD
2
AVDD
2
AVDD
4
AVDD
2
Figure 3. Unbuffered External Reference Drive—Internal Reference Disabled
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX1421CCM-TD | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1421ECM | 制造商:Maxim Integrated Products 功能描述:48 PINS TQFP PKG - Bulk |
| MAX1421ECM+ | 制造商:Maxim Integrated Products 功能描述:IC ADC LOW POWER 12BIT 3.3V SMD |
| MAX1421ECM+D | 功能描述:模数转换器 - ADC 12-Bit 40Msps 3.3V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1421ECM+TD | 功能描述:模数转换器 - ADC 12-Bit 40Msps 3.3V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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