参数资料
型号: MAX15046BAEE+T
厂商: Maxim Integrated Products
文件页数: 17/24页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 16-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.1MHz
占空比: 87.5%
电源电压: 4.5 V ~ 40 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 16-LSSOP(0.154",3.90mm 宽)裸露焊盘
包装: 带卷 (TR)
MAX15046
40V, High-Performance, Synchronous
Buck Controller
V IN ESR V FB
R F = OSC O OUT OUT
f Z1 =
f Z2 =
The total loop gain, which is the product of the modulator
gain and the error-amplifier gain at f O , is:
1
1) GAIN MOD × GAIN EA =
So :
1
× × × g M × R F =
V OSC (2 π × f O × L OUT ) V OUT
Solving for R F :
V × ( 2 π × f × L ) × V
V FB × V IN × g M × ESR
2) Set a midband zero (f Z1 ) at 0.75 x f PO (to cancel one
of the LC poles):
Type III Compensation Network (Figure 4)
When using a low-ESR tantalum or ceramic type, the
ESR-induced zero frequency is usually above the tar-
geted zero crossover frequency (f O ). Use Type III com-
pensation. Type III compensation provides two zeros
and three poles at the following frequencies:
1
2 π × R F × C F
1
2 π × C I × (R 1 + R I )
Two midband zeros (f Z1 and f Z2 ) cancel the pair of com-
plex poles introduced by the LC filter:
f P1 = 0
= 0.75 × f PO
f Z1
=
1
2 π × R F × C F
f P1 introduces a pole at zero frequency (integrator) for
nulling DC output-voltage errors:
Solving for C F :
f P2 =
1
2 π × R I × C I
C F =
f P3 =
2 π × R F ×
1
2 π × R F × f PO × 0.75
3) Place a high-frequency pole at f P1 = 0.5 x f SW (to
attenuate the ripple at the switching frequency f SW )
and calculate C CF using the following equation:
Depending on the location of the ESR zero (f ZO ), use f P2
to cancel f ZO , or to provide additional attenuation of the
high-frequency output ripple:
1
C F × C CF
C F + C CF
V OUT
R 1
C CF =
1
π × R F × f SW -
1
C F
f P3 attenuates the high-frequency output ripple.
Place the zeros and poles such that the phase margin
peaks around f O .
Ensure that R F >> 2/g M and the parallel resistance of
R 1 , R 2 , and R I is greater than 1/g M . Otherwise, a 180 N
phase shift is introduced to the response making the
loop unstable.
Use the following compensation procedures:
f =
= 0.8 × f PO
2 π × R F × C F
R 2
V REF
g M
R F
C F
COMP
C CF
1) With R F >> 10k I , place the first zero (f Z1 ) at 0.8 x
f PO :
1
Z1
Figure 3. Type II Compensation Network
Maxim Integrated
17
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