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| 型号： | MAX15109EWP+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 12/19页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 8A 20WLP |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 固定 |
| 输出数： | 1 |
| 输出电压： | 可编程 |
| 输入电压： | 2.7 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1MHz |
| 电流 - 输出： | 8A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 包装： | * |
| 供应商设备封装： | * |
High-Efficiency, 8A, Current-Mode Synchronous
Step-Down Switching Regulator with VID Control
Applications Information
Setting the Output Voltage
The output voltage is selected by using the VID0 and VID1
control inputs. Table 1 summarizes the output voltages.
Table 1. Output Voltages
VID0 VID1 VOLTAGE (V)
where f SW is the internally fixed 1MHz switching fre-
quency, and D I L is the estimated inductor ripple current
(typically set to 0.3 x I LOAD ). In addition, the peak induc-
tor current, I L_PK , must always be below the high-side
current-limit value, I HSCL , and the inductor saturation
current rating, I L_SAT .
Ensure that the following relationship is satisfied:
0
0
0
1
0.9
0.8
L_PK
I = I LOAD +
1
2
× ? I L < MIN(I HSCL ,I L_SAT )
1 0 0.725
1 1 0.675
Inductor Selection
A large inductor value results in reduced inductor ripple
current, leading to a reduced output ripple voltage. A
high-value inductor is of a larger physical size with a
Input Capacitor Selection
For a step-down converter, the input capacitor C IN helps
to keep the DC input voltage steady, in spite of discon-
tinuous input AC current. Use low-ESR capacitors to
minimize the voltage ripple due to ESR.
Size C IN using the following formula:
× OUT
higher series resistance (DCR) and a lower saturation
current rating. Choose inductor values to produce a
ripple current equal to 30% of the load current. Choose
C IN
=
I LOAD
f SW × ? V IN_RIPPLE
V
V IN
the inductor with the following formula:
V OUT OUT ?
× ? 1-
f SW × ? I L
V IN
L
=
? V
?
? ?
FEEDBACK
DIVIDER
V OUT
FB
ERROR AMPLIFIER
C
POWER MODULATOR
COMPENSATION
V IN
RAMP
g MC
OUTPUT FILTER
AND LOAD
COMP
Q HS
V OUT
CONTROL
LOGIC
L
DCR
g MV
R OUT
R C
*C CC
PWM
COMPARATOR
Q LS
I L
ESR
R LOAD
C OUT
C C
V COMP
G MOD
V OUT
SS
R OUT = A VEA /g MV
*C CC IS OPTIONAL.
I L
NOTE: THE G MOD STAGE SHOWN ABOVE MODELS THE AVERAGE CURRENT OF
THE INDUCTOR INJECTED INTO THE OUTPUT LOAD. THIS REPRESENTS A
SIMPLIFICATION FOR THE POWER MODULATOR STAGE DRAWN ABOVE.
Figure 1. Peak Current-Mode Regulator Transfer Model
12
_____________________________________________________________________________________
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