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参数资料
| 型号： | MAX15109EWP+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 13/19页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 8A 20WLP |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 固定 |
| 输出数： | 1 |
| 输出电压： | 可编程 |
| 输入电压： | 2.7 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1MHz |
| 电流 - 输出： | 8A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 包装： | * |
| 供应商设备封装： | * |
High-Efficiency, 8A, Current-Mode Synchronous
Step-Down Switching Regulator with VID Control
I RMS I O ×
I =
× t ON
2AV
Make sure that the selected capacitance can accom-
modate the input ripple current given by:
V OUT × (V IN - V OUT )
V IN
If necessary, use multiple capacitors in parallel to meet
the RMS current rating requirement.
Output Capacitor Selection
Use low-ESR ceramic capacitors to minimize the voltage
ripple due to ESR. Use the following formula to estimate
the total output voltage peak-to-peak ripple:
Skip Mode Frequency and Output Ripple
In skip mode, the switching frequency (f SKIP ) and output
ripple voltage (V OUT-RIPPLE ) shown in Figure 3 are cal-
culated as follows:
t ON is a fixed time by design (330ns, typ); the peak
inductor current reached is:
V IN ? V OUT
SKIP ? LIMIT
t OFF1 is the time needed for the inductor current to reach
the zero-crossing (~0A):
V OUT OUT ? ? ?
× ? 1-
? × ? R ESR_COUT +
f SW × L ?
8 × f SW OUT ?
× C
V IN ? ?
? V OUT =
? V 1
?
t OFF1 =
L × I SKIP-LIMIT
V OUT
C SS = SS
L × ( I SKIP-LIMIT - I LOAD ) × ?
+
? V IN - V OUT
V OUT ?
? Q OUT =
? Q OUT
Select the output capacitors to produce an output ripple
voltage that is less than 2% of the set output voltage.
Output Voltage Transition Timing
The IC features programmable output voltage transition
timing control. The regulator tracks the voltage on the
SS pin that is set with a current-limited (10μA) VID DAC.
A small capacitor at SS can therefore be used to set the
transition timing for startup and VID transitions.
I x ? t
? V OUT
where I SS is the soft-start current of 10 F A, δV OUT is the
output-voltage transition, and δt is the transition time.
During t ON and t OFF1 , the output capacitor stores a
charge equal to:
2 ? 1 1 ?
?
2
During t OFF2 (= n x t CK , number of clock cycles
skipped), the output capacitor loses this charge:
t OFF2
= →
I LOAD
L × ( I SKIP-LIMIT - I LOAD ) × ?
+
? V IN - V OUT
V OUT ?
When using large C OUT capacitance values, the high-
side current limit can trigger during the soft-start period.
To ensure the correct soft-start time, t SS , choose C SS
large enough to satisfy:
t OFF2 =
2 ? 1 1 ?
2 × I LOAD
?
C SS OUT =
>> C
f SKIP =
V OUT × I SS
(I HSCL_MIN -I OUT ) × V FB
I HSCL_MIN is the minimum high-side switch current-limit
value.
Finally, frequency in skip mode is:
1
t ON + t OFF1 + t OFF2
Output ripple in skip mode is:
( I SKIP-LIMIT LOAD ) × t ON + R
ESR,COUT SKIP-LIMIT LOAD )
× ( I - I
L × I SKIP-LIMIT
+ R ESR,COUT ? × ( I SKIP-LIMIT - I LOAD )
C OUT × ( V IN OUT )
?
? ?
? ?
V REF_EXT
R SS
C SS
SS
MAX15109
? ?
V OUT-RIPPLE = V COUT-RIPPLE + V ESR-RIPPLE =
-I
C OUT
V OUT-RIPPLE =
-V
Figure 2. Setting Soft-Start Time
Size C OUT based on the above formula to limit output
ripple in skip mode.
______________________________________________________________________________________
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