参数资料
型号: MAX16031ETM+T
厂商: Maxim Integrated Products
文件页数: 35/41页
文件大小: 0K
描述: IC SYSTEM MON EEPROM 48-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 多压监控器
监视电压数目: 8
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 可调节/可选择
电压 - 阀值: 8 种可选阀值组合
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-WFQFN 裸露焊盘
供应商设备封装: 48-TQFN-EP(7x7)
包装: 带卷 (TR)
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
Table 14. Miscellaneous Settings (continued)
REGISTER
ADDRESS
5Eh
EEPROM
MEMORY
ADDRESS
DEh
BIT
RANGE
[7:0]
DESCRIPTION
Firmware Version. 8 bits of memory for user-defined firmware version number.
Configuration Lock:
[0]
Write a ‘1’ to r5Fh[0] to toggle this register bit.
0 = Register and EEPROM configuration unlocked.
1 = Register and EEPROM configuration locked.
5Fh
DFh
[1]
[7:2]
Fault Log EEPROM Lock Flag (set automatically after fault log is triggered):
Write a ‘1’ to r5Fh[1] to toggle this register bit.
0 = EEPROM is not locked. A triggered fault log stores fault information to EEPROM.
1 = A fault log has been triggered. Write a ‘1’ to this bit to clear the flag and allow a
new fault log to be triggered.
Not used.
Table 15. Setting the I 2 C/SMBus Slave
Address
JTAG Serial Interface
The MAX16031/MAX16032 contain an IEEE ? 1149.1-
compliant JTAG port in addition to the I 2 C/SMBus-com-
A1
GND
GND
GND
N.C.
N.C.
N.C.
DBP
DBP
DBP
A0
GND
N.C.
DBP
GND
N.C.
DBP
GND
N.C.
DBP
BUS ADDRESS
0011000
0011001
0011010
0101001
0101010
0101011
1001100
1001111
1001110
patible serial bus. Either interface may be used to access
internal memory; however, only one interface is allowed to
run at a time. All digital I/Os on the MAX16031/MAX16032
are IEEE 1149.1 boundary-scan compliant, and contain
the typical JTAG boundary scan cells that allow the
inputs/outputs to be polled or forced high/low using stan-
dard JTAG instructions. The MAX16031/MAX16032 con-
tain extra JTAG instructions and registers not included in
the JTAG specification that provide access to internal
memory. The extra instructions are: LOAD ADDRESS,
WRITE, READ, REBOOT, SAVE, and USERCODE. The
extra registers are: memory address, memory write,
memory read, and user-code data. See Figure 6 for a
Special Commands
The MAX16031/MAX16032 provide software reboot and
fault log commands. A software reboot initiates the
boot-up sequence, which normally occurs at POR.
During boot-up, EEPROM configuration data is copied
to registers. To initiate a software reboot, send 0xFC
using the send byte format. A software-initiated fault log
is functionally the same as a hardware-initiated fault
log. During a fault log, ADC registers and fault informa-
tion are logged in EEPROM. To trigger a software initi-
ated fault log, send 0xFD using the send byte format.
block diagram of the JTAG interface.
Test Access Port (TAP) Controller State Machine
The TAP controller is a finite state machine that
responds to the logic level at TMS on the rising edge of
TCK. See Figure 7 for a diagram of the finite state
machine.
Test-Logic-Reset: At power-up, the TAP controller is in
the test-logic-reset state. The instruction register con-
tains the IDCODE instruction. All system logic of the
device operates normally.
IEEE is a registered service mark of teh Institute of Electrical and Electronics, Inc.
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