参数资料
型号: MAX17082GTL+T
厂商: Maxim Integrated Products
文件页数: 15/48页
文件大小: 0K
描述: IC CTLR PWM DUAL IMVP-6.5 40TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: Quick-PWM™
应用: 控制器, Intel IMVP-6+,IMVP-6.5?
输入电压: 4.5 V ~ 5.5 V
输出数: 1
输出电压: 0.013 V ~ 1.5 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(5x5)
包装: 带卷 (TR)
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Pin Description (continued)
PIN
4
5
6
7
8
9
10
11
12
NAME
ILIM
TIME
V CC
CCI
FB
FBAC
GNDS
CSN2
CSP2
FUNCTION
Valley Current-Limit Adjustment Input. The valley current-limit threshold voltage at CSP_ to CSN_
equals precisely 1/10 of the differential TIME to ILIM voltage over a 0.1V to 0.5V range (10mV to 50mV
current-sense range). The negative current-limit threshold is nominally -125% of the corresponding
valley current-limit threshold. Connect ILIM directly to V CC to set the default current-limit threshold
setting of 22.5mV (typ) nominal.
Slew-Rate Adjustment Pin. TIME regulates to 2.0V and the load current determines the slew rate of the
internal error-amplifier target. The sum of the resistance between TIME and GND (R TIME ) determines the
nominal slew-rate:
SLEW RATE = (12.5mV/μs) x (71.5k /RTIME)
The guaranteed R TIME range is between 35.7k
and 178k . This “nominal” slew rate applies to VID
transitions and to the transition from boot mode to VID. If the VID DAC inputs are clocked, the slew rate for
all other VID transitions is set by the rate at which they are clocked, up to a maximum slew rate equal to
the nominal slew rate defined above.
The startup and shutdown slew rates are always 1/8 of nominal slew rate in order to minimize surge
currents.
MAX17021: If both DPRSLPVR and DPRSTP are pulled high, then the slew rate is reduced to 1/4 of nominal.
MAX17082/MAX17482: If SLOW is low, then the slew rate is reduced to 1/2 of nominal.
Controller Analog Bias Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with 1μF minimum.
Current-Balance Compensation. Connect a 470pF capacitor between CCI and the positive side of the
feedback remote sense. CCI is internally forced low in shutdown.
Remote Feedback-Sense Input. Normally shorted to FBAC and connected to the VCC_SENSE pin of the
CPU socket through the load-line gain resistor (see the FBAC pin description). FB internally connects
to the error amplifier and integrator.
Voltage-Positioning Transconductance Amplifier Output. Connect a resistor R FB between FBAC and the
positive side of the feedback remote sense to set the DC steady-state droop based on the voltage-
positioning gain requirement:
R FB = R DROOP /(R SENSE x G m(FBAC) )
where R DROOP is the desired voltage-positioning slope and G m(FBAC) = 600 μS (typ). R SENSE is the
value of the current-sense resistors that are used to provide the (CSP_, CSN_) current-sense voltages. If
lossless sensing is used, R SENSE = R L . In this case, consider making R FB a resistor network that
includes an NTC thermistor to minimize the temperature dependence of the voltage-positioning slope.
FBAC is high impedance in shutdown.
Remote Ground-Sense Input. Normally connected to the VSS_SENSE pin of the CPU socket. GNDS
internally connects to a transconductance amplifier that fine tunes the output voltage—compensating
for voltage drops from the regulator ground to the load ground.
Negative Current-Sense Input for Phase 2. Connect CSN2 to the negative terminal of the inductor
current-sensing resistor or directly to the negative terminal of the inductor if the lossless DCR sensing
method is used (see Figure 4).
Positive Current-Sense Input for Phase 2. Connect CSP2 to the positive terminal of the inductor current-
sensing resistor or directly to the positive terminal of the filtering capacitor used when the lossless
DCR sensing method is used (see Figure 4). Short CSP2 to V CC for dedicated one-phase operation.
______________________________________________________________________________________
15
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