参数资料
型号: MAX17082GTL+T
厂商: Maxim Integrated Products
文件页数: 17/48页
文件大小: 0K
描述: IC CTLR PWM DUAL IMVP-6.5 40TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: Quick-PWM™
应用: 控制器, Intel IMVP-6+,IMVP-6.5?
输入电压: 4.5 V ~ 5.5 V
输出数: 1
输出电压: 0.013 V ~ 1.5 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(5x5)
包装: 带卷 (TR)
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Pin Description (continued)
PIN
20
21
22
23
24
25
26
27
28
29
30
NAME
PHASEGD
BST2
LX2
DH2
DL2
VRHOT
V DD
DL1
DH1
LX1
BST1
FUNCTION
Phase-Good Current-Balance Open-Drain Output. Used to signal the system that one of the two
phases either has a fault condition or is not matched with the other. Detection is done by identifying
the need for a large on-time difference between phases in order to achieve or move towards current
balance. PHASEGD is low in shutdown.
PHASEGD is forced high impedance whenever the slew-rate controller is active (output-voltage
transitions).
PHASEGD is forced high impedance while in one-phase operation (DPRSLPVR = high or PSI = low).
Boost Flying-Capacitor Connection for Phase 2. BST2 provides the upper supply rail for the DH2 high-
side gate driver. An internal switch between V DD and BST2 charges the flying capacitor while the low-
side MOSFET is on (DL2 pulled high and LX2 pulled to ground).
Inductor Connection for Phase 2. LX2 is the internal lower supply rail for the DH2 high-side gate driver.
Also used as an input to the controller ’s zero-crossing comparator for phase 2.
High-Side Gate-Driver Output for Phase 2. DH2 swings from LX2 to BST2. The controller pulls DH2 low
in shutdown.
Low-Side Gate-Driver Output for Phase 2. DL2 swings from GND to V DD . DL2 is forced low in skip mode
after detecting an inductor current zero crossing. DL2 is forced low during one-phase operation ( PSI =
GND or CSP2 = V CC ).
Open-Drain Output of Internal Comparator. VRHOT is pulled low when the voltage at THRM goes below
1.5V (30% of V CC ). VRHOT is high impedance in shutdown.
Driver Supply Voltage Input. V DD is the supply voltage used to internally power the low-side gate
drivers and refresh the BST_ flying capacitors during the off-times. Connect V DD to the 4.5V to 5.5V
system supply voltage. Bypass V DD to the system power ground with a 1 μF each or greater ceramic
capacitor.
Low-Side Gate-Driver Output for Phase 1. DL1 swings from GND to V DD . DL1 is forced high when an output
overvoltage fault is detected, overriding any negative current-limit condition that might be present. DL1 is
forced low after soft-shutdown or in skip mode after detecting an inductor current zero crossing.
High-Side Gate-Driver Output for Phase 1. DH1 swings from LX1 to BST1. The controller pulls DH1 low
in shutdown.
Inductor Connection for Phase 1. LX1 is the internal lower supply rail for the DH1 high-side gate driver.
Also used as an input to the controller ’s zero-crossing comparator for phase 1.
Boost Flying-Capacitor Connection for Phase 1. BST1 provides the upper supply rail for the DH1 high-
side gate driver. An internal switch between V DD and BST1 charges the flying capacitor while the low-
side MOSFET is on (DL1 is pulled high and LX1 is pulled to ground).
IMVP-6+ Slew-Rate Select Input. This 1.0V logic input signal from the IMVP-6+ system is usually the
logical complement of the DPRSLPVR signal. However, the IMVP-6+ specification supports a special
slow C4 exit condition that allows both DPRSTP and DPRSLPVR to be pulled high simultaneously.
When this occurs, the voltage-transition slew rate reduces to 1/4 the nominal (R TIME -based) slew rate
31
DPRSTP
(MAX17021)
SLOW
(MAX17082/
MAX17482)
for the duration of this logic condition. The slew rate returns to normal when either DPRSLPVR or
DPRSTP is pulled low:
DPRSLPVR DPRSTP SLEW RATE
0 0 Nominal slew rate
0 1 Nominal slew rate
1 0 Nominal slew rate
1 1 Slew rate reduced to 1/4 of nominal
IMVP-6.5 Slew-Rate Select Input. This 1.0V logic input signal selects between the nominal and “slow ”
(half of nominal rate) slew rates. When SLOW is forced high, the selected nominal slew rate is set by
the TIME resistance as defined above. When SLOW is forced low, the slew rate is reduced to half the
nominal slew rate.
______________________________________________________________________________________
17
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