参数资料
型号: MAX17082GTL+T
厂商: Maxim Integrated Products
文件页数: 44/48页
文件大小: 0K
描述: IC CTLR PWM DUAL IMVP-6.5 40TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: Quick-PWM™
应用: 控制器, Intel IMVP-6+,IMVP-6.5?
输入电压: 4.5 V ~ 5.5 V
输出数: 1
输出电压: 0.013 V ~ 1.5 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(5x5)
包装: 带卷 (TR)
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
PD ( N H Switching ) = ?
? ? I
η TOTAL
?
? ? GATE ?
C V f
? V OUT ? ? ? I LOAD ? 2
? V IN ( MAX ) ? ? ? ? η TOTAL ?
? ?
? ? I
?
? V
PD ( N H Re sistive ) = ? OUT ? ? LOAD ? R DS ( ON )
For most applications, nontantalum chemistries (ceram-
ic, aluminum, or OS-CON) are preferred due to their
resistance to inrush surge currents typical of systems
with a mechanical switch or connector in series with the
input. If the Quick-PWM controller is operated as the
second stage of a two-stage power-conversion system,
tantalum input capacitors are acceptable. In either con-
figuration, choose an input capacitor that exhibits less
than +10°C temperature rise at the RMS input current
for optimal circuit longevity.
Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (> 20V) AC adapters. Low-
current applications usually require less attention.
The high-side MOSFET (N H ) must be able to dissipate
the resistive losses plus the switching losses at both
V IN(MIN) and V IN(MAX) . Calculate both these sums.
Ideally, the losses at V IN(MIN) should be approximately
equal to losses at V IN(MAX) , with lower losses in
between. If the losses at V IN(MIN) are significantly high-
er than the losses at V IN(MAX) , consider increasing the
size of N H (reducing R DS(ON) but with higher C GATE ).
Conversely, if the losses at V IN(MAX) are significantly
higher than the losses at V IN(MIN) , consider reducing
the size of N H (increasing R DS(ON) to lower C GATE ). If
V IN does not vary over a wide range, the minimum
power dissipation occurs where the resistive losses
equal the switching losses.
Choose a low-side MOSFET that has the lowest possible
on-resistance (R DS(ON) ), comes in a moderate-sized
package (i.e., one or two 8-pin SOs, DPAK, or D 2 PAK),
and is reasonably priced. Make sure that the DL_ gate
driver can supply sufficient current to support the gate
charge and the current injected into the parasitic gate-
to-drain capacitor caused by the high-side MOSFET
turning on; otherwise, cross-conduction problems might
occur (see the MOSFET Gate Drivers section).
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET (N H ), the worst-
case power dissipation due to resistance occurs at the
minimum input voltage:
2
? V IN ? ? η TOTA L ?
where η TOTAL is the total number of phases.
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
However, the R DS(ON) required to stay within package
power dissipation often limits how small the MOSFET
can be. Again, the optimum occurs when the switching
losses equal the conduction (R DS(ON) ) losses. High-
side switching losses do not usually become an issue
until the input is greater than approximately 15V.
Calculating the power dissipation in high-side MOSFET
(N H ) due to switching losses is difficult since it must
allow for difficult quantifying factors that influence the
turn-on and turn-off times. These factors include the
internal gate resistance, gate charge, threshold volt-
age, source inductance, and PCB layout characteris-
tics. The following switching-loss calculation provides
only a very rough estimate and is no substitute for
breadboard evaluation, preferably including verification
using a thermocouple mounted on N H :
? V IN ( MAX ) I LOAD f SW ? ? Q G ( SW ) ?
?
2
+ OSS IN SW
2
where C OSS is the N H MOSFET’s output capacitance,
Q G(SW) is the charge needed to turn on the N H
MOSFET, and I GATE is the peak gate-drive source/sink
current (2.2A typ).
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied due to the squared term in the C x
V IN 2 x ? SW switching-loss equation. If the high-side
MOSFET chosen for adequate R DS(ON) at low-battery
voltages becomes extraordinarily hot when biased from
V IN(MAX) , consider choosing another MOSFET with
lower parasitic capacitance.
For the low-side MOSFET (N L ), the worst-case power
dissipation always occurs at maximum input voltage:
?
PD ( N L Re sistive ) = ? 1- ? ? ? ? ? R DS ( ON )
The worst case for MOSFET power dissipation occurs
under heavy overloads that are greater than
I LOAD(MAX) but are not quite high enough to exceed
44
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