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参数资料
| 型号： | MAX17528GTJ+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 17/41页 |
| 文件大小： | 0K |
| 描述： | IC CTLR PWM VID PS 1PH 32-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 系列： | Quick-PWM™ |
| 应用： | 控制器，Intel IMVP-6.5? GMCH |
| 输入电压： | 4.5 V ~ 5.5 V |
| 输出数： | 1 |
| 输出电压： | 0.01 V ~ 1.5 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 供应商设备封装： | 32-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
Pin Description (continued)
PIN
28
NAME
VRHOT
FUNCTION
Active-Low Open-Drain Output of Internal Comparator. VRHOT is pulled low when the voltage at
THRM goes below 1.5V (30% of V CC ). VRHOT is high-impedance in shutdown.
Slew-Rate Adjustment Pin. TIME regulates to 2.0V and the load current determines the slew rate of
the internal error-amplifier target. The sum of the resistance between TIME and GND (R TIME )
determines the nominal slew rate:
Slew rate = (12.5mV/μs) x (71.5k /R TIME )
29
TIME
The guaranteed R TIME range is between 35.7k
and 178k . This nominal slew rate applies to VID
transitions and to the transition from boot mode to VID. If the VID DAC inputs are clocked, the slew
rate for all other VID transitions is set by the rate at which they are clocked, up to a maximum slew
rate equal to the nominal slew rate defined above.
The startup and shutdown slew rates are always 1/8 of nominal slew rate to minimize surge currents.
If SLOW is high, the slew rate is reduced to 1/2 of nominal.
Valley Current-Limit Adjustment Input. The valley current-limit threshold voltage at CSP to CSN
equals precisely 1/10 the differential TIME to ILIM voltage over a 0.1V to 0.5V range (10mV to 50mV
30
31
32
—
ILIM
V CC
CCV
EP (GND)
current-sense range). The negative current-limit threshold is nominally -125% of the corresponding
valley current-limit threshold. Connect ILIM directly to V CC to set the default current-limit threshold
setting of 22.5mV (typ) nominal.
Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with 1μF minimum.
Integrator Capacitor Connection. Connect a capacitor (C CCV ) from CCV to GND to set the
integration time constant. Choose the capacitor value according to:
16 x (C CCV /G m(CCV) ) x f SW >> 1
where G m(CCV) = 320μS (max) is the integrator’s transconductance and f SW is the switching
frequency set by the R TON value.
The integrator is internally disabled during any downward output-voltage transition that occurs in
pulse-skipping mode, and remains disabled until the transition blanking period expires and the
output reaches regulation (error amplifier transition detected).
Exposed Pad (Back Side) and Analog Ground. Internally connected to GND. Connect to the ground
plane through a thermally enhanced via.
______________________________________________________________________________________
17
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