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参数资料
| 型号： | MAX17528GTJ+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 28/41页 |
| 文件大小： | 0K |
| 描述： | IC CTLR PWM VID PS 1PH 32-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 系列： | Quick-PWM™ |
| 应用： | 控制器，Intel IMVP-6.5? GMCH |
| 输入电压： | 4.5 V ~ 5.5 V |
| 输出数： | 1 |
| 输出电压： | 0.01 V ~ 1.5 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 供应商设备封装： | 32-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
t TRAN =
The MAX17528 automatically controls the current to the
minimum level required to complete the transition in the
calculated time. The slew-rate controller uses an inter-
nal capacitor and current-source programmed by
R TIME to transition the output voltage. The total transi-
tion time depends on R TIME , the voltage difference,
and the accuracy of the slew-rate controller (C SLEW
accuracy). The slew rate is not dependent on the total
output capacitance, as long as the surge current is less
than the current limit. For all dynamic VID transitions,
the transition time (t TRAN ) is given by:
V NEW ? V OLD
( dV TARGET / dt )
where dV TARGET /dt = 12.5mV/μs x 71.5k ? /R TIME is the
slew rate, V OLD is the original output voltage, and
V NEW is the new target voltage. See TIME Slew-Rate
Accuracy in the Electrical Characteristics table for
slew-rate limits. For soft-start and shutdown, the con-
troller automatically reduces the slew rate to 1/8.
The output voltage tracks the slewed target voltage,
making the transitions relatively smooth. Excluding the
load current, the average inductor current required to
make an output voltage transition is:
I L ? C OUT × ( dV TARGET / dt )
ACTIVE VID
CPU CORE
VOLTAGE
where dV TARGET /dt is the required slew rate and C OUT
is the total output capacitance.
IMVP-6.5 Low-Power Sleep Transition
The IMVP-6.5 CPU enters a low-power state to con-
serve power (Figure 5). The processor enters this state
by initially setting the core voltage to the LFM voltage
level (no LSB stepping). Upon reaching the LFM volt-
age level, the processor asserts DPRLPVR, which is
connected to SKIP as shown in Figure 1, signaling that
a very low current state has been entered. However,
the processor can still lower the core voltage by LSB
increments to further reduce power consumption under
this very low-power sleep state. The processor exits the
sleep state by pulling DPRSLVPR low and ramping up
the core voltage by LSB increments. During all VID
transitions, the MAX17528 blanks PWRGD (forced high
impedance) and CLKEN (forced low) until 20μs after
the internal target (which moves at the slew rate set by
R TIME ) reaches the selected VID code.
HFM VID
LFM VID
VID (D0–D6)
LFM VID
POSSIBLE VID CHANGE
HFM VID
DPRSLPVR
PULSE SKIPPING
1-PHASE FORCED PWM
PWRGD
CLKEN
DH
BLANK HIGH IMPEDANCE
BLANK LOW
t BLANK
20 μ s typ
BLANK HIGH IMPEDANCE
BLANK LOW
t BLANK
20 μ s typ
NOTE: DPRSLPVR = SKIP.
Figure 5. IMVP-6.5 Sleep Transition
28
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