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| 型号： | MAX17528GTJ+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 37/41页 |
| 文件大小： | 0K |
| 描述： | IC CTLR PWM VID PS 1PH 32-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 系列： | Quick-PWM™ |
| 应用： | 控制器，Intel IMVP-6.5? GMCH |
| 输入电压： | 4.5 V ~ 5.5 V |
| 输出数： | 1 |
| 输出电压： | 0.01 V ~ 1.5 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 供应商设备封装： | 32-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
The minimum current-limit threshold must be high
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The val-
ley of the inductor current occurs at I LOAD(MAX) minus
half the ripple current; therefore:
In CPU V CORE converters and other applications where
the output is subject to large-load transients, the output
capacitor’s size typically depends on how much ESR is
needed to prevent the output from dipping too low
under a load transient. Ignoring the sag due to finite
I VALLEY LOAD ( MAX ) ? 1 ?
> I
?
( R ESR PCB ) ≤ ? I
+ R
where:
?
?
LIR ?
2 ?
capacitance:
V STEP
LOAD ( MAX )
DCR × CSP ? CSN
I VALLEY =
V LIMIT
R SENSE
=
V LIMIT
R
R LX ? CSN
In non-CPU applications, the output capacitor’s size
often depends on how much ESR is needed to maintain
an acceptable level of output ripple voltage. The output
ripple voltage of a step-down controller equals the total
? ?
R ESR ≤ ?
? V RIPPLE
R FB =
f ESR ≤ SW
where R SENSE is the sensing resistor and R CSP-CSN /
R LX-CSN is the ratio of resistor-divider with DCR-
sensing approach.
Voltage Positioning and
Loop Compensation
Voltage positioning dynamically lowers the output volt-
age in response to the load current, reducing the out-
put capacitance and processor ’s power dissipation
requirements. The controller uses a transconductance
amplifier to set the transient and DC output voltage
droop (Figure 3) as a function of the load. This adjusta-
bility allows flexibility in the selected current-sense
resistor value or inductor DCR, and allows smaller cur-
rent-sense resistance to be used, reducing the overall
power dissipated.
Steady-State Voltage Positioning
Connect a resistor (R FB ) between FB and V OUT to set
the DC steady-state droop (load line) based on the
required voltage-positioning slope (R DROOP ):
R DROOP
R SENSE G m ( FB )
where the effective current-sense resistance (R SENSE )
depends on the current-sense method (see the Current
Sense section), and the voltage-positioning amplifier’s
transconductance (G m(FB) ) is typically 600μS as
defined in the Electrical Characteristics table. When the
inductors’ DCR is used as the current-sense element
(R SENSE = R DCR ), the current-sense design should
inductor ripple current multiplied by the output capaci-
tor’s ESR. The maximum ESR to meet ripple require-
ments is:
V IN f SW L
? ? ( V IN ? V OUT ) V OUT ? ?
where f SW is the switching frequency. The actual
capacitance value required relates to the physical size
needed to achieve low ESR, as well as to the chemistry
of the capacitor technology. Thus, the capacitor is usu-
ally selected by ESR and voltage rating rather than by
capacitance value (this is true of polymer types).
When using low-capacity ceramic filter capacitors,
capacitor size is usually determined by the capacity
needed to prevent V SAG and V SOAR from causing
problems during load transients. Generally, once
enough capacitance is added to meet the overshoot
requirement, undershoot at the rising load edge is no
longer a problem (see the V SAG and V SOAR equations
in the Transient Response section).
Output Capacitor Stability Considerations
For Quick-PWM controllers, stability is determined by
the value of the ESR zero relative to the switching fre-
quency. The boundary of instability is given by the fol-
lowing equation:
f
π
where:
include a thermistor to minimize the temperature
dependence of the voltage-positioning slope as shown
in Figure 1.
f ESR =
1
2 π R EFF C OUT
Output Capacitor Selection
The output filter capacitor must have low enough effec-
and:
R EFF = R ESR + R DROOP + R PCB
tive series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR
to satisfy stability requirements.
where C OUT is the total output capacitance, R ESR is the
total ESR, R DROOP is the voltage-positioning slope, and
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