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参数资料
| 型号： | MAX17582GTM+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 14/42页 |
| 文件大小： | 0K |
| 描述： | IC CTLR PWM 2PH IMVP-6.5 48-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 系列： | Quick-PWM™ |
| 应用： | 控制器，Intel IMVP-6.5? |
| 输入电压： | 4.5 V ~ 5.5 V |
| 输出数： | 1 |
| 输出电压： | 0.01 V ~ 1.5 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-TQFN-EP（6x6） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页当前第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页
Dual-Phase, Quick-PWM Controller for
IMVP-6.5 CPU Core Power Supplies
Pin Description (continued)
PIN
9
10
11
12, 24,
37
13
15
16
17
NAME
FB
FBAC
GNDS
N.C.
CSN2
CSP2
SHDN
DPRSLPVR
FUNCTION
Remote Feedback-Sense Input. Normally shorted to FBAC and connected to the VCC_SENSE pin of the
CPU socket through the load-line gain resistor (see the FBAC pin description). FB internally connects
to the error amplifier and integrator.
Voltage-Positioning Transconductance Amplifier Output. Connect a resistor R FB between FBAC and the
positive side of the feedback remote sense to set the DC steady-state droop based on the voltage-
positioning gain requirement:
R FB = R DROOP /(R SENSE x G m(FBAC) )
where R DROOP is the desired voltage-positioning slope and G m(FBAC) = 600 μS (typ). R SENSE is the
value of the current-sense resistors that are used to provide the (CSP_, CSN_) current-sense voltages. If
lossless sensing is used, R SENSE = R L . In this case, consider making R FB a resistor network that
includes an NTC thermistor to minimize the temperature dependence of the voltage-positioning slope.
FBAC is high impedance in shutdown.
Remote Ground-Sense Input. Normally connected to the VSS_SENSE pin of the CPU socket. GNDS
internally connects to a transconductance amplifier that fine tunes the output voltage—compensating
for voltage drops from the regulator ground to the load ground.
Internally Not Connected
Negative Current-Sense Input for Phase 2. Connect CSN2 to the negative terminal of the inductor
current-sensing resistor or directly to the negative terminal of the inductor if the lossless DCR sensing
method is used (see Figure 3).
Positive Current-Sense Input for Phase 2. Connect CSP2 to the positive terminal of the inductor current-
sensing resistor or directly to the positive terminal of the filtering capacitor used when the lossless
DCR sensing method is used (see Figure 3). Short CSP2 to V CC for dedicated 1-phase operation.
Shutdown Control Input. This input cannot withstand the battery voltage. Connect to V CC for normal
operation. Connect to ground to put the IC into its 1 μA max shutdown state. During startup, the output
voltage is ramped up to the boot voltage slowly at a slew rate that is 1/8 the slew rate set by the TIME
resistor. During the transition from normal operation to shutdown, the output voltage is ramped down at
the same slow slew rate. Forcing SHDN to 11V~13V disables undervoltage protection, clears the fault
latch, disables transient phase overlap, and disables the BST_ charging switches. Do not connect
SHDN to > 13V.
Pulse-Skipping Control Input. This 1.0V logic input signal indicates power usage and sets the operating
mode of the MAX17582. When DPRSLPVR is forced high, the controller immediately enters the automatic
pulse-skipping mode. The controller returns to forced-PWM mode when DPRSLPVR is forced low and the
output is in regulation. The PWRGD upper threshold is blanked during any downward output-voltage
transition that occurs when the controller is in pulse-skipping mode, and stays blanked until the transition-
related PWRGD blanking period is complete and the output reaches regulation.
The MAX17582 is in 2-phase pulse-skipping mode during startup and while in boot mode, but is in
forced-PWM mode during the transition from boot mode to VID mode plus 20 μs, and during soft-
shutdown, irrespective of the DRPSLPVR logic level.
DPRSLPVR and PSI together determine the operating mode and the number of active phases as shown
in the following truth table:
DPRSLPVR
PSI
MODE AND PHASES
1 0 Very low current (1-phase pulse skipping)
1 1 Low current (approximately 3A) (1-phase pulse skipping)
0 0 Intermediate power potential (1-phase PWM)
0 1 Max power potential (2- or 1-phase PWM as configured at CSP2)
14
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