参数资料
型号: MAX17582GTM+T
厂商: Maxim Integrated Products
文件页数: 4/42页
文件大小: 0K
描述: IC CTLR PWM 2PH IMVP-6.5 48-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: Quick-PWM™
应用: 控制器,Intel IMVP-6.5?
输入电压: 4.5 V ~ 5.5 V
输出数: 1
输出电压: 0.01 V ~ 1.5 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 48-WFQFN 裸露焊盘
供应商设备封装: 48-TQFN-EP(6x6)
包装: 带卷 (TR)
Dual-Phase, Quick-PWM Controller for
IMVP-6.5 CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V IN = 10V, V CC = V DD = V SHDN = V PGDIN = V PSI = V ILIM = 5V, V3P3 = 3.3V, DPRSLPVR = GNDS = GND, V CSP1
= V CSN1 = V CSP2 = V CSN1 = 1.0000V, FB = FBAC, R FBAC = 3.57k Ω from FBAC to CSN1, D6–D0 = [0101000]; V SLOW = 5V; T A = 0°C
to +85°C , unless otherwise noted. Typical values are at T A = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
FAULT PROTECTION
Output Undervoltage-
Protection Threshold
Output Undervoltage-
Propagation Delay
CLKEN Startup Delay and
Boot Time Period
PWRGD Startup Delay
V UVP
t UVP
t BOOT
Measured at FB with respect to the voltage target
set by the VID code; see Table 4
FB forced 25mV below trip threshold
Measured from the time when FB reaches the
boot target voltage (Note 2)
Measured at startup from the time when CLKEN
goes low
-450
20
3
-400
10
60
6.5
-350
100
10
mV
μs
μs
ms
Lower threshold,
CLKEN and PWRGD
Threshold
Measured at FB with respect
to the voltage target set by
the VID code; see Table 4,
20mV hysteresis (typ)
falling edge
(undervoltage)
Upper threshold,
rising edge
-350
+150
-300
+200
-250
+250
mV
(overvoltage)
CLKEN and PWRGD Delay
PHASEGD Delay
FB forced 25mV outside the PWRGD trip
thresholds
V (CCI,FB) forced 25mV outside trip thresholds
10
10
μs
μs
CLKEN , PWRGD, and
PHASEGD Transition
Blanking Time
t BLANK
Measured from the time when FB reaches the
target voltage (Note 2)
20
μs
(VID Transitions)
PHASEGD Transition
Blanking Time (Phase 2
Enable Transitions)
CLKEN Output Low Voltage
CLKEN Output High
Voltage
PWRGD, PHASEGD Output
Low Voltage
PWRGD, PHASEGD
Leakage Current
CSN1 Pulldown Resistance
in Shutdown
Number of DH2 pulses for which PHASEGD is
blanked after phase 2 is enabled
Low state, I SINK = 3mA
High state, I SOURCE = 3mA
Low state, I SINK = 3mA
High-impedance state, PWRGD, PHASEGD forced
to 5V, T A = +25°C
SHDN = 0, measured after soft-shutdown
completed (DL_ = low)
V3P3 -
0.4
32
10
0.4
0.4
1
Pulses
V
V
V
μA
V CC Undervoltage Lockout
(UVLO) Threshold
V UVLO(VCC)
Rising edge, 65mV typical hysteresis,
controller disabled below this level
4.05
4.27
4.48
V
4
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