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| 型号： | MAX17582GTM+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 16/42页 |
| 文件大小： | 0K |
| 描述： | IC CTLR PWM 2PH IMVP-6.5 48-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 系列： | Quick-PWM™ |
| 应用： | 控制器，Intel IMVP-6.5? |
| 输入电压： | 4.5 V ~ 5.5 V |
| 输出数： | 1 |
| 输出电压： | 0.01 V ~ 1.5 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-TQFN-EP（6x6） |
| 包装： | 带卷 (TR) |
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Dual-Phase, Quick-PWM Controller for
IMVP-6.5 CPU Core Power Supplies
Pin Description (continued)
PIN
32
33
34
35
36
38
39 –45
46
48
—
NAME
DL1
PGND1
DH1
LX1
BST1
SLOW
D0 –D6
CSP1
CSN1
EP
FUNCTION
Low-Side Gate-Driver Output for Phase 1. DL1 swings from GND to V DD . DL1 is forced low after soft-
shutdown or in skip mode after detecting an inductor current zero crossing.
Power Ground
High-Side Gate-Driver Output for Phase 1. DH1 swings from LX1 to BST1. The controller pulls DH1 low
in shutdown.
Inductor Connection for Phase 1. LX1 is the internal lower supply rail for the DH1 high-side gate driver.
Also used as an input to the controller ’s zero-crossing comparator for phase 1.
Boost Flying-Capacitor Connection for Phase 1. BST1 provides the upper supply rail for the DH1 high-
side gate driver. An internal switch between V DD and BST1 charges the flying capacitor while the low-
side MOSFET is on (DL1 is pulled high and LX1 is pulled to ground).
IMVP-6.5 Slew-Rate Select Input. This 1.0V logic input signal selects between the nominal and “slow ”
(half of nominal rate) slew rates. When SLOW is forced high, the selected nominal slew rate is set by
the TIME resistance as defined above. When SLOW is forced low, the slew rate is reduced to half the
nominal slew rate.
Low-Voltage VID DAC Code Input. The D0 –D6 inputs do not have internal pullups. These 1.0V logic
inputs are designed to interface directly with the CPU. The output voltage is set by the VID code
indicated by the logic-level voltages on D0 –D6 (see Table 4).
Positive Current-Sense Input for Phase 1. Connect CSP1 to the positive terminal of the inductor current-
sensing resistor or directly to the positive terminal of the filtering capacitor used when the lossless
DCR sensing method is used (see Figure 3).
Negative Current-Sense Input for Phase 1. Connect CSN1 to the negative terminal of the inductor
current-sensing resistor or directly to the negative terminal of the inductor if the lossless DCR sensing
method is used (see Figure 3).
Under V CC UVLO conditions and after soft-shutdown is completed, CSN1 is internally pulled to GND
through a 10
FET to discharge the output.
Exposed Pad. Internally connected to GND. Connect to the ground plane through a thermally
enhanced via.
Detailed Description
Table 1 lists the component selection for standard
applications. Table 2 lists component suppliers for the
MAX17582.
Free-Running, Constant-On-Time PWM
Controller with Input Feed-Forward
The Quick-PWM control architecture is a pseudo-fixed-
frequency, constant-on-time, current-mode regulator
with voltage feed-forward (Figure 2). This architecture
relies on the output filter capacitor’s ESR to act as the
current-sense resistor, so the output ripple voltage pro-
vides the PWM ramp signal. The control algorithm is
simple: the high-side switch on-time is determined sole-
ly by a one-shot whose period is inversely proportional
to input voltage and directly proportional to output volt-
age, or the difference between the main and secondary
inductor currents (see the On-Time One-Shot section).
Another one-shot sets a minimum off-time. The on-time
one-shot triggers when the error comparator goes low,
the inductor current of the selected phase is below the
valley current-limit threshold, and the minimum off-time
one-shot times out. The controller maintains 180° out-of-
phase operation by alternately triggering the main and
secondary phases after the error comparator drops
below the output-voltage set point.
16
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