参数资料
型号: MAX1858EEG+
厂商: Maxim Integrated Products
文件页数: 15/21页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 24-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
PWM 型: 电压模式
输出数: 2
频率 - 最大: 660kHz
占空比: 90%
电源电压: 4.75 V ~ 23 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 24-SSOP(0.154",3.90mm 宽)
包装: 管件
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
A FB / LX = = SET
V OUT S LC OUT ESR OUT + 1
+ SR C
V LX
V 1 + SR ESR C OUT
? SET
V OUT V OUT S LC OUT + 1
removed from the output filter capacitors by a sudden
load step. The amount of output-voltage sag is also a
function of the maximum duty factor, which can be cal-
culated from the minimum off-time and switching fre-
quency:
2
2
V FB V 1 + sR ESR C OUT
L ( I LOAD 1 - I LOAD 2 ) 2 ? ?
? ? V OUT ? ?
? ? ? V IN SW ?
? + t OFF ( MIN ) ?
? ?
? ? V IN - V OUT ?
V SAG =
2 C OUT OUT ? ? ? - t OFF ( MIN ) ?
? ? ? V IN SW ?
? ?
g M _ COMP 1 + SR COMP C COMP _ A
1 + SR COMP COMP _ B
V SET 1 + SR ESR C OUT
× ×
V OUT
+ 1
S LC
f
?
V
f
where t OFF(MIN) is the minimum off-time (see the
Therefore:
A L ? ×
SC COMP _ A C
2
OUT
×
V IN
V RAMP
Electrical Characteristics ), and f SW is set by R OSC (see
the Setting the Switching Frequency section).
Compensation
Each voltage-mode controller section employs a
transconductance error amplifier whose output is the
compensation point of the control loop. The control
loop is shown in Figure 7. For frequencies much lower
For an ideal integrator, this loop gain approaches infini-
ty at DC. In reality the g M amplifier has a finite output
impedance which imposes a finite, but large, loop gain.
It is this large loop gain that provides DC load accura-
cy. The dominant pole occurs due to the integrator, and
for this analysis, it can be approximated to occur at DC.
R COMP creates a zero at:
than Nyquist, the PWM block can be simplified to a
voltage amplifier. Connect R COMP_ and C COMP_A from
COMP to GND to compensate the loop (see Figure 7).
The inductor, output capacitor, compensation resistor,
f Z _ COMP _ A =
1
2 π × R COMP _ C COMP _ A
and compensation capacitors determine the loop sta-
bility. Since the inductor and output capacitor are cho-
The inductor and capacitor form a double pole at:
sen based on performance, size, and cost, select the
compensation resistor and capacitors to optimize con-
trol-loop stability.
f LC =
1
2 π × LC OUT
To determine the loop gain (A L ), consider the gain from
FB to COMP (A COMP/FB ), from COMP to LX
(A LX/COMP ), and from LX to FB (A FB/LX ). The total loop
gain is:
A L = A COMP / FB × A LX / COMP × A FB / LX
At some higher frequency the output capacitor ’ s
impedance becomes insignificant compared to its ESR,
and the LC system becomes more like an LR system,
turning a double pole into a single pole. This zero
occurs at:
A COMP / FB = ?
1 + sR COMP C COMP _ A
1 + sR COMP COMP _ B
f ESR =
where:
×
V FB SC COMP
V COMP g M _ COMP
C
1
2 π × R ESR C OUT
A final pole is added using C COMP_B to reduce the
gain and attenuate noise after crossover. This pole
(f COMP_B ) occurs at:
assuming an ideal integrator, and assuming that
C COMP_B is much less than C COMP_A .
f COMP _ B =
1
2 π × R COMP C COMP _ B
A LX / COMP =
V LX
V COMP
=
V IN
V RAMP
Figure 8 shows a Bode plot of the poles and zeros in
their relative locations.
for frequencies lower than Nyquist.
Near crossover the following approximations can be
made to simplify the loop-gain equation:
______________________________________________________________________________________
15
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