参数资料
型号: MAX1904EAI+T
厂商: Maxim Integrated Products
文件页数: 19/33页
文件大小: 0K
描述: IC CNTRLR PWR SPLY LN 28-SSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,000
应用: 控制器,笔记本电脑电源系统
输入电压: 4.2 V ~ 30 V
输出数: 4
输出电压: 2.5 V ~ 5 V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-SSOP(0.209",5.30mm 宽)
供应商设备封装: 28-SSOP
包装: 带卷 (TR)
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
Interference due to switching noise is reduced in PWM
mode by ensuring a constant switching frequency, thus
concentrating the emissions at a known frequency out-
side the system audio or IF bands. Choose an oscillator
frequency for which switching frequency harmonics
don ’ t overlap a sensitive frequency band. If necessary,
synchronize the oscillator to a tight-tolerance external
clock generator. To extend the output-voltage regula-
tion range, constant operating frequency is not main-
tained under overload or dropout conditions (see the
Dropout Operation section).
PWM mode ( SKIP = high) forces two changes upon the
PWM controllers. First, it disables the minimum-current
comparator, ensuring fixed-frequency operation.
Second, it changes the detection threshold for reverse
current limit from 0 to -100mV, allowing the inductor cur-
rent to reverse at light loads. This results in fixed-fre-
quency operation and continuous inductor-current flow.
This eliminates discontinuous-mode inductor ringing and
improves cross regulation of transformer-coupled multi-
ple-output supplies, particularly in circuits that don ’ t use
additional secondary regulation via SECFB or V DD .
In most applications, tie SKIP to GND to minimize qui-
escent supply current. VL supply current with SKIP high
is typically 30mA, depending on external MOSFET gate
capacitance and switching losses.
Internal Digital Soft-Start Circuit
Soft-start allows a gradual increase of the internal cur-
rent-limit level at startup to reduce input surge currents.
Both SMPSs contain internal digital soft-start circuits,
each controlled by a counter, a digital-to-analog con-
verter (DAC), and a current-limit comparator. In shut-
down or standby mode, the soft-start counter is reset to
zero. When an SMPS is enabled, its counter starts
counting oscillator pulses, and the DAC begins incre-
menting the comparison voltage applied to the current-
limit comparator. The DAC output increases from 0 to
100mV in five equal steps as the count increases to
512 clocks. As a result, the main output capacitor
charges up relatively slowly. The exact time of the out-
put rise depends on output capacitance and load cur-
rent, and is typically 600μs with a 500kHz oscillator.
Dropout Operation
Dropout (low input-output differential operation) is
enhanced by stretching the clock pulse width to
increase the maximum duty factor. The algorithm fol-
lows: If the output voltage (V OUT ) drops out of regula-
tion without the current limit having been reached, the
SMPS skips an off-time period (extending the on-time).
At the end of the cycle, if the output is still out of regula-
tion, the SMPS skips another off-time period. This
action can continue until three off-time periods are
skipped, effectively dividing the clock frequency by as
much as four.
The typical PWM minimum off-time is 300ns, regardless
of the operating frequency. Lowering the operating fre-
quency raises the maximum duty factor above 97%.
Adjustable-Output Feedback
(Dual Mode FB)
Fixed, preset output voltages are selected when FB_ is
connected to ground. Adjusting the main output volt-
age with external resistors is simple for any of the
MAX1901/MAX1902/MAX1904, through resistor divi-
ders connected to FB3 and FB5 (Figure 2). Calculate
the output voltage with the following formula:
V OUT = V REF (1 + R1 / R2)
where V REF = 2.5V nominal.
The nominal output should be set approximately 1% or
2% high to make up for the MAX1901/MAX1902/
MAX1904 -2% typical load-regulation error. For exam-
ple, if designing for a 3.0V output, use a resistor ratio
that results in a nominal output voltage of 3.05V. This
slight offsetting gives the best possible accuracy.
Recommended normal values for R2 range from 5k ? to
100k ? . To achieve a 2.5V nominal output, simply con-
nect FB_ directly to CSL_.
Remote output-voltage sensing, while not possible in
fixed-output mode due to the combined nature of the
voltage-sense and current-sense inputs (CSL3 and
CSL5), is easy to do in adjustable mode by using the top
of the external resistor-divider as the remote sense point.
When using adjustable mode, it is a good idea to
always set the “ 3.3V output ” to a lower voltage than the
“ 5V output. ” The 3.3V output must always be less than
VL, so that the voltage on CSH3 and CSL3 is within the
common-mode range of the current-sense inputs. While
VL is nominally 5V, it can be as low as 4.7V when lin-
early regulating, and as low as 4.2V when automatically
bootstrapped to CSH5.
Secondary Feedback Regulation Loop
(SECFB or V DD )
A flyback-winding control loop regulates a secondary
winding output, improving cross-regulation when the
primary output is lightly loaded or when there is a low
input-output differential voltage. If V DD or SECFB falls
below its regulation threshold, the low-side switch is
turned on for an extra 0.75μs. This reverses the induc-
______________________________________________________________________________________
19
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