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参数资料
| 型号： | MAX2160ETL+ |
| 厂商： | Maxim Integrated |
| 文件页数： | 16/25页 |
| 文件大小： | 0K |
| 描述： | IC TUNER ISDB-T LOW IF 40TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 50 |
| 系列： | * |
| 频率： | 470MHz ~ 770MHz |
| 应用： | 手机 |
| 电流 - 接收： | 44mA |
| 数据接口： | PCB，表面贴装 |
| 存储容量： | * |
| 天线连接器： | PCB，表面贴装 |
| 电源电压： | 2.7 V ~ 3.3 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（6x6） |
| 包装： | 托盘 |
ISDB-T Single-Segment Low-IF Tuners
Table 10. Status Byte-1 Register
BIT NAME
X
CP[1:0]
PWR
VASA
VASE
BIT LOCATION
(0 = LSB)
7, 6, 5
4, 3
2
1
0
FUNCTION
Unused.
Reflect the charge-pump current setting. See Table 3 for CP[1:0] definition.
Logic-high indicates power has been cycled, but the device has the default programming. A STOP
condition while in read mode resets this bit.
Indicates whether VCO automatic selection was successful.
0 = indicates the autoselect function is disabled or unsuccessful VCO selection
1 = indicates successful VCO automatic selection
Status indicator for the autoselect function.
0 = indicates the autoselect function is active
1 = indicates the autoselect process is inactive
Table 11. Status Byte-2 Register
BIT NAME
VCO[1:0]
VSB[2:0]
ADC[2:0]
BIT LOCATION
(0 = LSB)
7, 6
5, 4, 3
2, 1, 0
FUNCTION
Indicate which VCO has been selected by either the autoselect state machine or by manual
selection when the VAS state machine is disabled. See Table 4 for VCO[1:0] definition.
Indicate which sub-band of a particular VCO has been selected by either the autoselect state
machine or by manual selection when the VAS state machine is disabled. See Table 4 for VSB[2:0]
definition.
Indicate the 3-bit ADC conversion of the VCO tuning voltage (VTUNE).
2-Wire Serial Interface
The MAX2160/EBG uses a 2-wire I 2 C-compatible serial
interface consisting of a serial-data line (SDA) and a
serial-clock line (SCL). SDA and SCL facilitate bidirec-
tional communication between the MAX2160/EBG and
the master at clock frequencies up to 400kHz. The
master initiates a data transfer on the bus and gener-
ates the SCL signal to permit data transfer. The
MAX2160/EBG behave as a slave device that transfers
and receives data to and from the master. SDA and
SCL must be pulled high with external pullup resistors
(1k ? or greater) for proper bus operation.
One bit is transferred during each SCL clock cycle. A
minimum of nine clock cycles is required to transfer a
byte in or out of the MAX2160/EBG (8 bits and an
ACK/NACK). The data on SDA must remain stable dur-
ing the high period of the SCL clock pulse. Changes in
SDA while SCL is high and stable are considered con-
trol signals (see the START and STOP Conditions sec-
tion). Both SDA and SCL remain high when the bus is
not busy.
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), which is a high-to-low transition on SDA while
SCL is high. The master terminates a transmission with
a STOP condition (P), which is a low-to-high transition
on SDA while SCL is high.
Acknowledge and Not-Acknowledge Conditions
Data transfers are framed with an acknowledge bit
(ACK) or a not-acknowledge bit (NACK). Both the mas-
ter and the MAX2160/EBG (slave) generate acknowl-
edge bits. To generate an acknowledge, the receiving
device must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and
keep it low during the high period of the clock pulse.
16
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