参数资料
型号: MAX2160ETL+
厂商: Maxim Integrated
文件页数: 17/25页
文件大小: 0K
描述: IC TUNER ISDB-T LOW IF 40TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
系列: *
频率: 470MHz ~ 770MHz
应用: 手机
电流 - 接收: 44mA
数据接口: PCB,表面贴装
存储容量: *
天线连接器: PCB,表面贴装
电源电压: 2.7 V ~ 3.3 V
工作温度: -40°C ~ 85°C
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(6x6)
包装: 托盘
ISDB-T Single-Segment Low-IF Tuners
To generate a not-acknowledge condition, the receiver
allows SDA to be pulled high before the rising edge of
the acknowledge-related clock pulse, and leaves SDA
high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data trans-
fer happens if a receiving device is busy or if a system
fault has occurred. In the event of an unsuccessful data
transfer, the bus master must reattempt communication
at a later time.
Slave Address
The MAX2160/EBG have a 7-bit slave address that
must be sent to the device following a START condition
to initiate communication. The slave address is internal-
ly programmed to 1100000. The eighth bit (R/ W ) follow-
ing the 7-bit address determines whether a read or
write operation will occur.
The MAX2160/EBG continuously await a START condi-
tion followed by its slave address. When the device
recognizes its slave address, it acknowledges by
pulling the SDA line low for one clock period; it is ready
to accept or send data depending on the R/ W bit
(Figure 1).
SLAVE ADDRESS
Write Cycle
When addressed with a write command, the
MAX2160/EBG allow the master to write to a single reg-
ister or to multiple successive registers.
A write cycle begins with the bus master issuing a START
condition followed by the seven slave address bits and a
write bit (R/ W = 0). The MAX2160/EBG issue an ACK if
the slave address byte is successfully received. The bus
master must then send to the slave the address of the first
register it wishes to write to (see Table 1 for register
addresses). If the slave acknowledges the address, the
master can then write one byte to the register at the spec-
ified address. Data is written beginning with the most sig-
nificant bit. The MAX2160/EBG again issue an ACK if the
data is successfully written to the register. The master
can continue to write data to the successive internal reg-
isters with the MAX2160/EBG acknowledging each suc-
cessful transfer, or it can terminate transmission by
issuing a STOP condition. The write cycle will not termi-
nate until the master issues a STOP condition.
Figure 2 illustrates an example in which registers 0
through 2 are written with 0x0E, 0xD8, and 0xE1,
respectively.
S
1
1
0
0
0
0
0
R/W
ACK
P
SDA
SCL
1
2
3
4
5
6
7
8
9
Figure 1. MAX2160 Slave Address Byte
START
WRITE DEVICE
ADDRESS
R/W
ACK
WRITE REGISTER
ADDRESS
ACK
WRITE DATA TO
REGISTER 0x00
ACK
WRITE DATA TO
REGISTER 0x01
ACK
WRITE DATA TO
REGISTER 0x02
ACK
STOP
1100000
0
0x00
0x0E
0xD8
0xE1
Figure 2. Example: Write Registers 0 through 2 with 0x0E, 0xD8, and 0xE1, Respectively
______________________________________________________________________________________
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