参数资料
| 型号： | MAX3676EHJ+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 2/15页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK RECOVERY 32-TQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 360 |
| 类型： | 时钟和数据恢复（CDR），多路复用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 输入： | PECL |
| 输出： | PECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 622.08MHz |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-TQFP |
| 供应商设备封装： | 32-TQFP（5x5） |
| 包装： | 托盘 |
MAX3676
622Mbps, 3.3V Clock-Recovery and
Data-Retiming IC with Limiting Amplifier
10
______________________________________________________________________________________
Note that the LOL monitor is only valid when a data
stream is present on the inputs to the MAX3676. As a
result, LOL does not detect a loss-of-power condition
resulting from a loss of the incoming signal. See the
Loss-of-Power Monitor section for this type of indicator.
Input and Output Terminations
The MAX3676 digital data and clock I/Os (DDI+, DDI-,
SDO+, SDO-, SCLK+, and SCLK-) are designed to
interface with PECL signal levels. It is important to bias
these ports appropriately. A circuit that provides a
Thevenin equivalent of 50
Ω to VCC - 2V should be used
with fixed-impedance transmission lines for proper ter-
mination. Make sure that the differential outputs have
balanced loads.
The digital data input signals (DDI+ and DDI-) are dif-
ferential inputs to an emitter-coupled pair. As a result,
the MAX3676 can accept differential input signals as
low as 250mV. These inputs can also be driven single-
ended by externally biasing DDI- to the center of the
voltage swing.
The MAX3676’s performance can be greatly affected
by circuit board layout and design. Use good high-fre-
quency design techniques, including minimizing
ground inductance and using fixed-impedance trans-
mission lines on the data and clock signals. Power-sup-
ply decoupling should be placed as close to VCC as
possible. Take care to isolate the input from the output
signals to reduce feedthrough.
Applications Information
Driving the Limiting Amplifier
Single-Ended
There are three important requirements for driving the
limiting amplifier from a single-ended source (Figure 5):
1) There must be no DC-coupling to the ADI+ and ADI-
inputs. DC levels at these inputs disrupt the offset-
correction loop.
2) The terminating resistor RT (50
Ω) must be referenced
to the ADI- input to minimize common-mode coupling
problems.
3) The low-frequency cutoff for the limiting amplifier
is determined by either CIN and the 2.5k
Ω input
impedance or Cb/2 together with RT. With Cb = 0.22μF
and RT = 50
Ω,the low-frequency cutoff is 29kHz.
ACQUIRE
NO DATA
LOP
OUTPUT
LEVEL
LOCKED
TIME
LOL
Figure 4. Loss-of-Lock Output
CIN
5.6nF
Cb
0.22
μF
Cb
0.22
μF
RT
50
Ω
2.5k
Ω
ADI+
ADI-
MAX3676
Figure 5. Single-Ended Input Termination
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX3676EHJ+ | 功能描述:时钟发生器及支持产品 622Mbps 3.3V Clock Recovery RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MAX3676EHJ+T | 功能描述:时钟发生器及支持产品 622Mbps 3.3V Clock Recovery RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MAX3676EHJ-T | 功能描述:时钟发生器及支持产品 622Mbps 3.3V Clock Recovery RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MAX3677CTJ+ | 制造商:Microsemi Corporation 功能描述:+3.3V, LOW-JITTER CLOCK GEN W/MULT OUT - Trays 制造商:Microsemi Corporation 功能描述:Microsemi MAX3677CTJ+ Clocks - Timers 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CLOCK GENERATOR PROGR 32TQFN 制造商:Microsemi Corporation 功能描述:IC CLOCK GENERATOR PROGR 32TQFN |
| MAX3677CTJ+T | 制造商:Microsemi Corporation 功能描述:+3.3V, LOW-JITTER CLOCK GEN W/MULT OUT - Tape and Reel |
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