参数资料
型号: MAX3676EHJ+
厂商: Maxim Integrated Products
文件页数: 3/15页
文件大小: 0K
描述: IC CLOCK RECOVERY 32-TQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 360
类型: 时钟和数据恢复(CDR),多路复用器
PLL:
主要目的: SONET/SDH
输入: PECL
输出: PECL
电路数: 1
比率 - 输入:输出: 2:2
差分 - 输入:输出: 是/是
频率 - 最大: 622.08MHz
电源电压: 3 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-TQFP
供应商设备封装: 32-TQFP(5x5)
包装: 托盘
MAX3676
622Mbps, 3.3V Clock-Recovery and
Data-Retiming IC with Limiting Amplifier
______________________________________________________________________________________
11
Reduced Power Consumption
Without the Limiting Amplifier
The limiting amplifier is biased independently from the
clock recovery circuitry. Grounding INSEL turns off the
limiting amplifier and selects the PECL DDI inputs.
Converting Average Optical Power
to Signal Amplitude
Many of the MAX3676’s specifications relate to input-
signal amplitude. When working with fiber optic
receivers, the input is usually expressed in terms of
average optical power and extinction ratio. The rela-
tions given in Table 2 and Figure 6 are helpful for con-
verting optical power to input signal when designing
with the MAX3676.
In an optical receiver, the input voltage to the limiting
amplifier can be found by multiplying the relationship in
Table 2 by the photodiode responsivity and transim-
pedance amplifier gain.
Optical Hysteresis
Power and hysteresis are often expressed in decibels.
By definition, decibels are always 10log (power). At the
inputs to the MAX3676 limiting amplifier, the power is
VIN2/R. If a receiver’s optical input power (x) increases
by a factor of two, and the preamplifier is linear, then the
voltage at the input to the MAX3676 also increases by a
factor of two.
The optical power increase is:
10log(2x/x) = 10log(2) = +3dB
At the MAX3676, the voltage increase is:
In an optical receiver, the decibel change at the
MAX3676 always equals 2x the optical decibel change.
The MAX3676’s typical voltage hysteresis is 3.0dB. This
provides an optical hysteresis of 1.5dB.
Jitter in Optical Receivers
Timing jitter, edge speeds, aberrations, optical disper-
sion, and attenuation all impact the performance of
high-speed clock recovery for SDH/SONET receivers
(Figure 7). These effects decrease the time available
for error-free data recovery by reducing the received
“eye opening” of nonreturn-to-zero (NRZ) transmitted
signals.
10
2
20
2
log
log(
)
log(
2V
/ R
V/ R
=
IN
()
=
))
=+6dB
TIME
P0
P1
PAVE
Figure 6. Optical Power Relations
Table 2. Optical-Power Relations*
*Assuming a 50% average input-data duty cycle.
SYMBOL
RELATION
Average
Power
PAVG
Extinction
Ratio
re
PARAMETER
Optical Power
of a “1”
P1
Optical Power
of a “0”
P0
Signal
Amplitude
PIN
P
= P0 + P1 / 2
AVG
()
r =
1 / P0
e
P
PP
r
AVG
e
12
1
=
+
P0
2P
/ r
1
AVG
e
=+
()
PP
P
r
IN
AVG
e
=
()
+
10
2
1
AMPLITUDE
EYE DIAGRAM WITH NO TIMING JITTER
EFFECTS OF TIMING JITTER ON EYE DIAGRAM
TIME
MIDPOINT
TIME
MIDPOINT
Figure 7. Eye Diagram With and Without Timing Jitter
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MAX3676EHJ+ 功能描述:时钟发生器及支持产品 622Mbps 3.3V Clock Recovery RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56
MAX3676EHJ+T 功能描述:时钟发生器及支持产品 622Mbps 3.3V Clock Recovery RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56
MAX3676EHJ-T 功能描述:时钟发生器及支持产品 622Mbps 3.3V Clock Recovery RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56
MAX3677CTJ+ 制造商:Microsemi Corporation 功能描述:+3.3V, LOW-JITTER CLOCK GEN W/MULT OUT - Trays 制造商:Microsemi Corporation 功能描述:Microsemi MAX3677CTJ+ Clocks - Timers 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CLOCK GENERATOR PROGR 32TQFN 制造商:Microsemi Corporation 功能描述:IC CLOCK GENERATOR PROGR 32TQFN
MAX3677CTJ+T 制造商:Microsemi Corporation 功能描述:+3.3V, LOW-JITTER CLOCK GEN W/MULT OUT - Tape and Reel