参数资料
型号: MAX5042ATN+T
厂商: Maxim Integrated Products
文件页数: 11/22页
文件大小: 0K
描述: IC PWR W/MOSFET HS 56-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 电源
电源电压: 20 V ~ 76 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 56-WFQFN 裸露焊盘
供应商设备封装: 56-TQFN-EP(8x8)
包装: 带卷 (TR)
Two-Switch Power ICs with Integrated
Power MOSFETs and Hot-Swap Controller
Pin Description (continued)
MAX5042
26
PIN
MAX5043
NAME
HSOK
FUNCTION
Hot-Swap OK (MAX5042 Only). HSOK ’s open-drain output is forced to NEGIN upon
hot-swap completion.
Hot-Swap Enable (MAX5042 Only). HSEN is the center point of the internal hot-swap
27
HSEN
UVLO divider. Use an external voltage-divider or a 100k ? pullup resistor to the most
positive rail to override.
Negative Supply Input (MAX5042 Only). NEGIN connects to the most negative input
28, 29
NEGIN
supply rail. NEGIN provides the hot-swap circuit’s most negative connection. NEGIN
is at the same potential as the IC substrate.
30
31
32
33
34
35
32
33
34
26, 28, 29,
31, 35
HSGATE
HSDRAIN
CSOUT
CSP
CSN
PWMNEG
Hot-Swap Gate (MAX5042 Only). Connect HSGATE to the gate of the external hot-
swap MOSFET.
Hot-Swap MOSFET Drain Sense (MAX5042 Only). Connect HSDRAIN to the drain of
the external hot-swap MOSFET.
Current-Sense Amplifier Output. The amplifier has a gain of 10. Connect CSOUT to
RAMP for current-mode control.
Positive Current-Sense Connection. Place the current-sense resistor as close as
possible to the device and use a Kelvin connection.
Negative Current-Sense Connection. Place the current-sense resistor as close as
possible to the device and use a Kelvin connection.
Analog Signal Return for the PWM Section
Driver Delay Adjust Connection. Connect a resistor and a 0.22μF capacitor from
DRVDEL to PWMNEG. The resistor at DRVDEL controls the skew between the
36
36
DRVDEL
PPWM signal and the power pulse applied to the internal power MOSFETs. Use in
conjunction with a secondary-side synchronous-rectifier controller. The skew allows
for the optimization of the synchronous-rectifier drive pulse.
37
38
39
41
37
38
39
41
PPWM
REG9
REG5
REG15
PWM Pulse Output. PPWM leads the internal power MOSFET pulse by an amount
determined with the resistor value at DRVDEL.
9V Internal Regulator Output. Use primarily as a source for the internal gate drivers.
Bypass REG9 to PWMNEG with a 1μF ceramic capacitor.
5V Internal Regulator Output. Bypass REG5 to PWMNEG with a 1μF ceramic
capacitor.
15V Startup Regulator Output. A voltage greater than 18V on REG15 disables the
regulator. Bypass REG15 to PWMNEG with at least one 1μF ceramic capacitor.
PWM Undervoltage Lockout. UVLO is the center point of the PWM undervoltage
46
46
UVLO
lockout divider. Use an external divider or a 100k ? pullup resistor to POSINPWM to
override. Connect the external resistor-divider network from POSINPWM to
PWMNEG.
______________________________________________________________________________________
11
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