where fIN represents the analog input frequency and
tAJ is the time of the clock jitter.
Clock jitter is especially critical for undersampling
applications. Consider the clock input as an analog
input and route away from any analog input or other
digital signal lines. The MAX5863 clock input operates
with an OVDD/2 voltage threshold and accepts a 50%
±15% duty cycle.
Reference Configurations
The MAX5863 features an internal precision 1.024V
bandgap reference that is stable over the entire power
supply and temperature range. The REFIN input pro-
vides two modes of reference operation. The voltage at
REFIN (VREFIN) sets reference operation mode (Table 4).
In internal reference mode, connect REFIN to VDD.
VREF is an internally generated 0.512V. COM, REFP,
and REFN are low-impedance outputs with VCOM =
VDD/2, VREFP = VDD/2 + VREF/2, and VREFN = VDD/2 -
VREF/2. Bypass REFP, REFN, and COM each with a
0.33F capacitor. Bypass REFIN to GND with a 0.1F
capacitor.
In buffered external reference mode, apply 1.024V
±10% at REFIN. In this mode, COM, REFP, and REFN
are low-impedance outputs with VCOM = VDD/2, VREFP
= VDD/2 + VREFIN/4, and VREFN = VDD/2 - VREFIN/4.
Bypass REFP, REFN, and COM each with a 0.33F
capacitor. Bypass REFIN to GND with a 0.1F capaci-
tor. In this mode, the DAC’s full-scale output voltage
and common-mode voltage are proportional to the
external reference. For example, if the VREFIN is
increased by 10% (max), the DACs’ full-scale output
voltage is also increased by 10% or
±440mV, and com-
mon-mode voltage increases by 10%.
Applications Information
Using Balun Transformer AC-Coupling
An RF transformer (Figure 7) provides an excellent
solution to convert a single-ended signal source to a
fully differential signal for optimum ADC performance.
Connecting the center tap of the transformer to COM
provides a VDD/2 DC level shift to the input. A 1:1 trans-
former can be used, or a step-up transformer can be
selected to reduce the drive requirements. In general,
the MAX5863 provides better SFDR and THD with fully
differential input signals than single-ended signals,
especially for high-input frequencies. In differential
mode, even-order harmonics are lower as both inputs
(IA+, IA-, QA+, QA-) are balanced, and each of the
ADC inputs only requires half the signal swing com-
pared to single-ended mode. Figure 8 shows an RF
transformer converting the MAX5863 DACs’ differential
analog outputs to single ended.
MAX5863
Ultra-Low-Power, High-Dynamic
Performance, 7.5Msps Analog Front End
______________________________________________________________________________________
19
Table 4. Reference Modes
VREFIN
REFERENCE MODE
>0. 8 x VDD
Internal reference mode. VREF is internally
generated to be 0.512V. Bypass REFP,
REFN, and COM each with a 0.33F
capacitor.
1.024V ±10%
Buffered external reference mode. An
external 1.024V ±10% reference voltage
is applied to REFIN. VREF is internally
generated to be VREFIN/2. Bypass REFP,
REFN, and COM each with a 0.33F
capacitor. Bypass REFIN to GND with a
0.1F capacitor.
Figure 7. Balun-Transformer Coupled Single-Ended to
Differential Input Drive for ADCs
COM
IA+
IA-
25
0.1
F
0.33
F
25
0.1
F
VIN
MAX5863
22pF
QA+
QA-
25
0.1
F
0.33
F
25
0.1
F
VIN
22pF