参数资料
型号: MAX5935EAX+
厂商: Maxim Integrated
文件页数: 22/44页
文件大小: 700K
描述: IC CTRLR POWER QUAD 36-SSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 30
类型: 以太网供电控制器(PoE)
应用: 远程外设(工业控制,相机,数据访问)
内部开关:
电源电压: -32 V ~ -60 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 36-BSOP(0.295",7.50mm 宽)
供应商设备封装: 36-SSOP
包装: 管件
Message Format for Reading
The MAX5935 reads using the MAX5935s internally
stored command byte as an address pointer, the same
way the stored command byte is used as an address
pointer for a write. The pointer auto-increments after
reading each data byte using the same rules as for a
write. Thus, a read is initiated by first configuring the
MAX5935s command byte by performing a write
(Figure 12). The master now reads n consecutive
bytes from the MAX5935, with the first data byte read
from the register addressed by the initialized command
byte (Figure 13). When performing read-after-write veri-
fication, remember to reset the command bytes
address because the stored control byte address auto-
increments after the write.
Operation with Multiple Masters
When the MAX5935 operates on a 2-wire interface with
multiple masters, a master reading the MAX5935
should use repeated starts between the write that sets
the MAX5935s address pointer, and the read(s) that
takes the data from the location(s). It is possible for
master 2 to take over the bus after master 1 has set up
the MAX5935s address pointer but before master 1
has read the data. If master 2 subsequently resets the
MAX5935s address pointer, then master 1s read may
be from an unexpected location.
Command Address Auto-Incrementing
Address auto-incrementing allows the MAX5935 to be
configured with fewer transmissions by minimizing the
number of times the command address needs to be
sent. The command address stored in the MAX5935
generally increments after each data byte is written or
read (Table 4). The MAX5935 is designed to prevent
overwrites on unavailable register addresses and unin-
tentional wraparound of addresses.
Register Map And Description
The interrupt register (Table 5) summarizes the event
register status and is used to send an interrupt signal
(INT goes low) to the controller. Writing a 1 to R1Ah[7]
clears all interrupt and events registers. A Reset sets
R00h to 00h.
INT_EN (R17h[7]) is a global interrupt mask (Table 6).
The MASK_ bits activate the corresponding interrupt
bits in register R00h. Writing a 0 to INT_EN (R17h[7])
disables the INT output.
A Reset sets R01h to AAA00A00b, where A is the state
of the AUTO input prior to the reset.
The power event register (Table 7) records changes in
the power status of the four ports. Any change in
PGOOD_ (R10h[7:4]) sets PG_CHG_ to 1. Any change
in the PWR_EN_ (R10h[3:0]) sets PWEN_CHG_ to 1.
PG_CHG_ and PWEN_CHG_ trigger on the edges of
PGOOD_ and PWR_EN_ and do not depend on the
actual level of the bits. The power event register has
two addresses. When read through the R02h address,
the content of the register is left unchanged. When read
through the CoR R03h address, the register content will
be cleared. A Reset sets R02h/R03h = 00h.
DET_END_/CL_END_ is set high whenever detection/
classification is completed on the corresponding port.
A 1 in any of the CL_END_ bits forces R00h[4] to 1. A 1
in any of the DET_END_ bits forces R00h[3] to 1. As
with any of the other events register, the detect event
register (Table 8) has two addresses. When read
through the R04h address, the content of the register is
left unchanged. When read through the CoR R05h
address, the register content will be cleared. A Reset
sets R04h/R05h = 00h.
LD_DISC_ is set high whenever the corresponding port
shuts down due to detection of load removal.
IMAX_FLT_ is set high when the port shuts down due to
an extended overcurrent event after a successful start-
up. A 1 in any of the LD_DISC_ bits forces R00h[2] to 1.
A 1 in any of the IMAX_FLT_ bits forces R00h[5] to 1.
As with any of the other events registers, the fault event
register (Table 9) has two addresses. When read
through the R06h address, the content of the register is
left unchanged. When read through the CoR R07h
address, the register content will be cleared. A reset
sets R06h/R07h = 00h.
If the port remains in current limit or the PGOOD condi-
tion is not met at the end of the startup period, the port
shuts down and the corresponding STRT_FLT_ is set to
1. A 1 in any of the STRT_FLT_ bits forces R00h[6] to 1.
IVC_ is set to 1 whenever the port current exceeds the
maximum allowed limit for the class (determined during
the classification process). A 1 in any of IVC_ forces
R00h[6] to 1. When the CL_DISC (R17h[2]) is set to 1,
the port will also limit the load current according to its
class as specified in the Electrical Characteristics table.
As with any of the other events registers, the startup
event register (Table 10) has two addresses. When
Quad Network Power Controller
for Power-Over-LAN
22   ______________________________________________________________________________________
COMMAND BYTE
ADDRESS RANGE
AUTO-INCREMENT BEHAVIOR
0x00 to 0x26
Command address will auto-
increment after byte read or written
0x26
Command address remains at 0x26
after byte written or read
Table 4. Auto-Increment Rules
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