参数资料
型号: MAX5935EAX+
厂商: Maxim Integrated
文件页数: 5/44页
文件大小: 700K
描述: IC CTRLR POWER QUAD 36-SSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 30
类型: 以太网供电控制器(PoE)
应用: 远程外设(工业控制,相机,数据访问)
内部开关:
电源电压: -32 V ~ -60 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 36-BSOP(0.295",7.50mm 宽)
供应商设备封装: 36-SSOP
包装: 管件
Quad Network Power Controller
for Power-Over-LAN
_______________________________________________________________________________________   5
ELECTRICAL CHARACTERISTICS (continued)
(AGND = +48V. V
EE
= 0V, V
DD
to DGND = +3.3V. All voltages are referenced to V
EE
, unless otherwise noted. Typical
values are at AGND = +48V, DGND = +48V, V
DD
= (DGND + 3.3V), T
A
= +25癈. Currents are positive when entering the pin and
negative otherwise.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
NIT
Internal Input Pullup/Pulldown
Resistor
R
DIN
Pullup (pulldown) resistor to V
DD
 (DGND) to set
default level
25
50
75
k&
Open-Drain Output Low
Voltage
V
OL
I
SINK
 = 15mA
0.4
V
Open-Drain Leakage
I
OL
Open-drain high impedance, V
O
= 3.3V
2
TIMING
Startup Time
t
START
Time during which a current limit set by V
SU_LIM
is allowed, starts when the GATE_ is turned on
(Note 8)
50
60
70
ms
Fault Time
t
FAULT
Maximum allowed time for an overcurrent
condition set by V
FLT_LIM
 after startup (Note 8)
50
60
70
ms
Port Turn-Off Time
t
OFF
Minimum delay between any port turning off,
does not apply in the case of a reset
0.5
0.75
1
ms
Detection Time
t
DET
Maximum time allowed before detection
is completed
320
ms
Midspan Mode Detection
Delay
t
DMID
2.0
2.4
s
Classification Time
t
CLASS
Time allowed for classification
40
ms
V
EEUVLO
 Turn-On Delay
t
DLY
Time V
AGND
 must be above the V
EEUVLO
thresholds before the device operates
2
4
ms
RSTR bits = 00
16 x
t
FAULT
RSTR bits = 01
32 x
t
FAULT
RSTR bits = 10
64 x
t
FAULT
Restart Timer
t
RESTART
Ti
m e a p or t has to w ai t
b efor e tur ni ng on after
 an
over cur r ent faul
t,
RS TR_E
N b i t = hi
g h
RSTR bits = 11
0
ms
Watchdog Clock Period
t
WD
Rate of decrement of the watchdog timer
164
ms
TIMING CHARACTERISTICS for 2-WIRE FAST MODE (Figures 5 and 6)
Serial Clock Frequency
f
SCL
(Note 9)
400
kHz
Bus Free Time Between a
STOP and a START Condition
t
BUF
(Note 9)
1.2
Hold Time for Start Condition
t
HD STA
(Note 9)
0.6
Low Period of the SCL Clock
t
LOW
(Note 9)
1.2
High Period of the SCL Clock
t
HIGH
(Note 9)
0.6
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