参数资料
型号: MAX5935EAX+
厂商: Maxim Integrated
文件页数: 29/44页
文件大小: 700K
描述: IC CTRLR POWER QUAD 36-SSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 30
类型: 以太网供电控制器(PoE)
应用: 远程外设(工业控制,相机,数据访问)
内部开关:
电源电压: -32 V ~ -60 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 36-BSOP(0.295",7.50mm 宽)
供应商设备封装: 36-SSOP
包装: 管件
sets a minimum duty cycle that protects the external
MOSFET from overheating during prolonged output
overcurrent conditions.
A reset sets R16h = 00h.
Setting CL_DISC to 1 (Table 20) enables port-over-
class current protection, where the MAX5935 scales
down the overcurrent limit (V
FLT_LIM
) according to the
port classification status. This feature provides protec-
tion to the system against PDs that violate their maxi-
mum class current allowance.
A reset sets R17h = 0xC0.
Power-enable pushbutton (Table 21) for SEMI and
MANUAL modes. Setting PWR_ON_ to 1 turns on
power to the corresponding port. Setting PWR_OFF_ to
1 turns off power to the port. PWR_ON is ignored when
the port is already powered and during shutdown.
PWR_OFF is ignored when the port is already off and
during shutdown. After execution, the bits reset to 0.
During detection or classification if PWR_ON_ goes
high, the MAX5935 gracefully terminates the current
operation and turn-on power to the port. The MAX5935
ignores the PWR_ON_ in AUTO mode. A reset sets
R19h = 00h.
Quad Network Power Controller
for Power-Over-LAN
______________________________________________________________________________________   29
ADDRESS = 15h
SYMBOL
BIT
R/W
DESCRIPTION
Reserved
7
R
Reserved
Reserved
6
R
Reserved
Reserved
5
R
Reserved
Reserved
4
R
Reserved
BCKOFF4
3
R/W    Enable Cadence timing on Port 4
BCKOFF3
2
R/W    Enable Cadence timing on Port 3
BCKOFF2
1
R/W    Enable Cadence timing on Port 2
BCKOFF1
0
R/W    Enable Cadence timing on Port 1
Table 18. Backoff Enable Register
ADDRESS = 16h
SYMBOL
BIT
R/W
DESCRIPTION
RSTR 1
7
R/W
Restart timer   ro  rammin   bit 1
R  TR
6
R/W
R
r  im  r  r   r  mmin    i
TSTART 1
5
R/W
Startu   timer   ro  rammin   bit 1
T  TART
4
R/W
r
im  r  r   r  mmin    i
TFA  LT 1
3
R/W
v  r   rr  n  im  r  r   r  mmin    i  1
TFAULT 0
2
R/W
Overcurrent timer   ro  rammin   bit 0
TDI
1
1
R/W
L
i    nn
im  r  r   r  mmin    i  1
TDISC 0
0
R/W
Load disconnect timer   ro  rammin   bit 0
Table 19. Timing Register
Bit[1:0]
RSTR
t
DISC
t
START
t
FAULT
00
16 x t
FAULT
t
DISC
 nominal
(350ms, typ)
t
START
 nominal
(60ms, typ)
t
FAULT
 nominal
(60ms, typ)
01
32 x t
FAULT
1/4 x t
DISC
 nominal
1/2 x t
START
 nominal
1/2 x t
FAULT
 nominal
10
64 x t
FAULT
1/2 x t
DISC
 nominal
2 x t
START
 nominal
2 x t
 nominal
11
0 x t
FAULT
2 x t
DISC
 nominal
4 x t
START
 nominal
4 x t
FA  LT
 nominal
Table 19a. Startup, Fault, and Load Disconnect Timers with Default Values in the
Register 27h and 28h
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