参数资料
型号: MAX5935EAX+
厂商: Maxim Integrated
文件页数: 27/44页
文件大小: 700K
描述: IC CTRLR POWER QUAD 36-SSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 30
类型: 以太网供电控制器(PoE)
应用: 远程外设(工业控制,相机,数据访问)
内部开关:
电源电压: -32 V ~ -60 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 36-BSOP(0.295",7.50mm 宽)
供应商设备封装: 36-SSOP
包装: 管件
Setting DET_EN_/CLASS_EN_ to 1 (Table 17) enables
load detection/classification, respectively. Detection
always has priority over classification. To perform clas-
sification without detection, set the DET_EN_ bit low
and CLASS_EN_ bit high.
In MANUAL mode, R14h works like a pushbutton. Set
the bits high to begin the corresponding routine. The bit
clears after the routine finishes.
When entering AUTO mode, R14h defaults to FFh.
When entering MANUAL mode, R14h defaults to 00h.
When entering SEMI mode, R1h is left unchanged but
is reset every time the software commands power off the
port. A reset or power-up sets R14h = AAAAAAAAb,
where A represents the latched-in state of the AUTO
input prior to the reset.
Quad Network Power Controller
for Power-Over-LAN
______________________________________________________________________________________   27
ADDRESS = 10h
SYMBOL
BIT
R/W
DESCRIPTION
P    D4
7
R
P  w  r-
n  i i  n  n P  r  4
PGOOD3
6
R
Power-  ood condition on Port 3
P
D2
5
R
P  w  r-
n  i i  n  n P  r  2
P
D1
4
R
P  w  r-
n  i i  n  n P  r  1
PWR_EN4
3
R
Power is enabled on Port 4
PWR EN
2
R
P  w  r i    n   l
n P  r
PWR_EN2
1
R
Power is enabled on Port 2
PWR_EN1
0
R
Power is enabled on Port 1
Table 13. Power Status Register
ADDRESS = 11h
SYMBOL
BIT
R/W
DESCRIPTION
Reserved
7
R
Reserved
R    rv
6
R
R    rv
A3
5
R
Device address A3   in latched in status
A2
4
R
D  vi
r
A2  in l    h    in
A1
3
R
Device address A1   in latched in status
A0
2
R
Device address A0   in latched in status
MID  PAN
1
R
MID  PAN in
l    h    in
AUTO
0
R
AUTO in  uts latched-in status
Table 14. Address Input Status Register
ADDRESS = 12h
SYMBOL
BIT
R/W
DESCRIPTION
P4 M1
7
R/W
M  DE 1  f  r    r  4
P4 M
6
R/W
M  DE    f  r    r  4
P3_M1
5
R/W
M0DE 1 for   ort 3
P   M
4
R/W
M  DE    f  r    r
P2_M1
3
R/W
M0DE 1 for   ort 2
P2_M0
2
R/W
M0DE 0 for   ort 2
P1 M1
1
R/W
M  DE 1  f  r    r  1
P1_M0
0
R/W
M0DE 0 for   ort 1
Table 15. Mode Register
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