参数资料
型号: MAX6960ATH+T
厂商: Maxim Integrated
文件页数: 15/34页
文件大小: 0K
描述: IC DRVR LED 8X8 44-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
显示器类型: LED
配置: 8 x 8(矩阵)
接口: 4 线串行
数字或字符: 任何数字类型
电流 - 电源: 7.5mA
电源电压: 2.7 V ~ 3.6 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 44-WFQFN 裸露焊盘
供应商设备封装: 44-TQFN-EP(7x7)
包装: 带卷 (TR)
MAX6960–MAX6963
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED Drivers
3-Wire Interface Data Lines
(ADDOUT and ADDIN)
One MAX6960 is designated the master device, and this
is allocated driver address 0. The master’s ADDIN pin is
connected to V+, identifying it as the first device. This
first MAX6960 should be the driver for the top-left pix-
Use of ADDOUT as Plane Change Interrupt
(IRQ)
When the plane counter is configured to automatic mode
(bit 6 of the global plane counter register is set) (Table
30), ADDOUT pulses low for a time of 512/OSC (nominally
122μs) at the start of every automatic plane change. This
els of the display panel.
The master ’s
signal can be used as an interrupt output from the display
ADDOUT pin is connected to the second MAX6960’s
ADDIN pin, and that MAX6960’s ADDOUT pin is connect-
ed to the third MAX6960’s ADDIN, and so on up to 256
MAX6960s. The last MAX6960’s ADDOUT pin is left open
circuit. The last MAX6960 should be the driver for the
bottom-right pixels of the display panel. The ADDOUT
is initialized low at the start of a 3-wire interface configura-
tion operation, and goes high (N + 1.5) ADDCLK periods
later, where n is the driver address of the MAX6960 (0 to
255). See Figures 1 and 2 for connection examples.
3-Wire Interface Clock (ADDCLK)
The ADDCLK pins for all MAX6960s are all connected
together. ADDCLK data rate is determined by OSC / 4,
nominally 1.048576 MHz. The ADDCLK pin for the master
MAX6960 (driver address 0) is always an output, and all
the other ADDCLKs are always inputs. ADDCLK is active
for exactly 256 clock cycles when a panel configuration is
being performed (on power-up reset, and after a write to
the global panel configuration register).
Table 8. Register Address Map
panel to the host to flag that the previous display plane is
now unused and can be written with a new image.
Multiplex Clock
The OSC input for all MAX6960s sharing a 3-wire interface
bus (but not necessarily a 4-wire interface bus) should be
driven by a common CMOS-level clock ranging between
1MHz and 8.5MHz. It is usually necessary to use an exter-
nal clock tree to fan out multiple clock drives when larger
numbers of MAX6960s are used because of the capaci-
tive loads. For example, each one of the eight outputs of a
standard 74HC541 octal buffer could drive 8 to 32
MAX6960 OSC inputs, depending on the layout used.
The recommended setting for OSC is 4.194303MHz. This
frequency sets the slow global plane counter resolution to
1s, and the fast global plane counter resolution to 1Hz.
REGISTER
COMMAND ADDRESS
HEX CODE
D15
D14
D13
D12
D11
D10
D9
D8
Driver Address (read only)
Pixel Intensity Scale
Panel Intensity
Digit 0 Intensity
Digit 1 Intensity
Fault
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0x00
0x01
0x02
0x03
0x04
0x05
0x06
Global Driver Indirect Address*
Global Display Indirect Address LSB*
Global Display Indirect Address
Global Plane Counter*
Global Clear Planes*
Global Panel Configuration*
Global Driver Devices*
Global Driver Rows*
R/ W
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
* When reading from the global registers, only the master MAX6960 (whose driver address is 0x00) responds.
Maxim Integrated
15
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