参数资料
型号: MAX6960ATH+T
厂商: Maxim Integrated
文件页数: 24/34页
文件大小: 0K
描述: IC DRVR LED 8X8 44-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
显示器类型: LED
配置: 8 x 8(矩阵)
接口: 4 线串行
数字或字符: 任何数字类型
电流 - 电源: 7.5mA
电源电压: 2.7 V ~ 3.6 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 44-WFQFN 裸露焊盘
供应商设备封装: 44-TQFN-EP(7x7)
包装: 带卷 (TR)
MAX6960–MAX6963
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED Drivers
Table 27. Panel Intensity Register Format
REGISTER
ADDRESS CODE
(HEX)
D7
D6
D5
REGISTER DATA
D4 D3
D2
D1
D0
0x02
0
0
0
0
0
0
0
0
2/256 (min on)
3/256
4/256
5/256
251/256
252/256
253/256
254/256
255/256 (max on)
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
1
1
1
1
0
1
1
0
0
1
0
0
1
1
1
0
1
0
1
1
0
1
0
1
Table 28. Global Driver Indirect Address Format
REGISTER
ADDRESS CODE
(HEX)
D7
D6
D5
REGISTER DATA
D4 D3
D2
D1
D0
Global driver indirect address
0x08
MSB
8-bit driver indirect address 0x00 to 0xFF
LSB
Planes/Intensity Control (Bit D7)
The planes/intensity (PI) control bit in the global panel
configuration register selects whether the display mem-
ory is configured as four planes with 1-bit-per pixel per
color-intensity control, or two planes with 2-bits-per
pixel per color-intensity control. This bit is fixed at zero
for the MAX6961 and MAX6963, and a write to this bit is
ignored for these parts.
Pixel Intensity Scale Register
The pixel intensity scale register (Table 24) sets the
graduation type used when 2-bits-per-pixel intensity
control is selected by setting the PI bit (Table 22). The
pixel level-intensity control can be set to be either
arithmetic (off, 1/3, 2/3, full) or geometric (off, 1/4, 1/2,
full). The setting is made on a digit-by-digit basis, so
each color on an RGY or RGB panel can use the most
appropriate graduation type.
Digit Intensity Control
The digit 0 and digit 1 intensity registers (Tables 25 and
26) set the fractions of the panel intensity PWM value
that are applied to the two display digits. The PWM for
each digit is calculated as n/256th of the panel intensity
value, where n is the value in the digit’s digit 0/1 intensi-
ty register. The digit 0/1 intensity registers enable con-
figuring relative adjustments in digit intensity, while the
24
display panel is still controlled as a whole by the panel
intensity. These adjustments are typically used to cali-
brate out luminosity differences between LEDs from dif-
ferent batches. They can also be used to color balance
RGY displays so that, for example, full panel intensity of
a red-green panel is a consistent orange hue.
Panel Intensity Control
Digital control of panel display brightness is provided
by an internal pulse-width modulator, which is con-
trolled by the panel intensity register (Table 27). The
modulator scales the average segment current in 253
steps from a maximum of 255/256 down to 2/256 of the
peak current. The maximum effective PWM duty cycle
for a digit is therefore 254/256, given by the maximum
255/256 digit intensity multiplied by the maximum
255/256 panel intensity. The minimum interdigit blank-
ing time is therefore 4/256 of a cycle, or 4/256 x 122μs
digit period = 1.91μs.
Peak-Segment Current Selection
The LED drive current can be selected between either
a 40mA peak per segment and a lower 20mA peak cur-
rent on a digit-by-digit basis using the R ISET0 and
R ISET1 pins. R ISET0 should be open circuit to select
20mA, or connected to GND to select 40mA segment
current for digit 0. R ISET1 selects segment current for
Maxim Integrated
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