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参数资料
| 型号： | MAX7307ALB+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 10/23页 |
| 文件大小： | 0K |
| 描述： | IC LED DRIVER LINEAR 10-UDFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 拓扑： | PWM |
| 输出数： | 4 |
| 内部驱动器： | 是 |
| 类型 - 主要： | 背光，LED 闪烁器 |
| 类型 - 次要： | 白色 LED |
| 频率： | 1MHz |
| 电源电压： | 1.62 V ~ 3.6 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-WFDFN |
| 供应商设备封装： | 10-uDFN（2x2） |
| 包装： | 带卷 (TR) |
| 工作温度： | -40°C ~ 125°C |
SMBus/I 2 C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
Slave Address
The MAX7307 is set to slave address 0x98 and the
MAX7306 can be set to one of four I 2 C slave addresses
0x98 to 0x9F, using the address input AD0 (see Table 5)
and is accessed over an I 2 C or SMBus serial interface.
The MAX7306 slave address is determined on each I 2 C
transmission, regardless of the transmission actually
addressing the device or not. The MAX7306 distin-
guishes whether address input AD0 is connected to
SDA, SCL, V DD , or GND during the transmission.
Therefore, the MAX7306 slave address can be config-
ured dynamically in an application without toggling the
device supply.
I/O Port Registers
The port I/O registers set the I/O ports, one register per
port (see Tables 6 and 7). Use the I/O port registers to
configure the ports individually as inputs, open-drain, or
push-pull outputs. Port P1 can only be configured as an
input or an open-drain output. The push-pull bit (D6) set-
ting for the port I/O register P1 is ignored.
I/O Input Port
Configure a port as an input by writing a logic-high to the
MSB (bit D7) of the port I/O register (see Table 6). To
obtain the logic level of the port input, read the port I/O
register bit, D0. This readback value is the instantaneous
logic level at the time of the read request if debounce is
Table 5. Slave-Address Selection
AD0 DEVICE ADDRESS
CONNECTION A6 A5 A4 A3 A2 A1
A0
R/ W
disabled for the port (port I/O register bit D2 = 0), or the
debounced result if debounce is enabled for the port
(port I/O register bit D2 = 1). See Figure 1 for input port
structure.
GND
V DD
SCL
SDA
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0/1
0/1
0/1
0/1
I/O Output Port
Configure a port as an output by writing a logic-low to the
MSB (bit D7) of the port I/O register. The device reads
back the logic level, PWM, or the blink setting of the port
(see Table 7).
Table 6. Port I/O Registers (I/O Port Set as an Input, Registers 0x01 to 0x04)
REGISTER BIT
D7
D6*
D5
D4, D3
D2
D1
D0
DESCRIPTION
Port I/O Set Bit
Port Supply
Reference
Transition Interrupt
Enable
Reserved
Debounce
Port Transition
State (Read-Only)
Port Status
(Read-Only)
VALUE
1
0
1
0
1
0
0
1
0
1
0
1
FUNCTION
Sets the I/O port as an input.
Refers the input to the V LA supply voltage.
Refers the input to the V DD supply voltage.
Disables the transition interrupt.
Enables the transition interrupt.
Do not write to these registers.
Disables debouncing of the input port.
Enables debouncing of the input port.
No transition has occurred since the last port read.
A transition has occurred since the last port read.
Port input is logic-low.
Port input is logic-high.
* Bit D6 controls the I/O’s supply reference for the MAX7307. The MAX7306 ignores bit D6.
10
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