参数资料
型号: MAX7307ALB+T
厂商: Maxim Integrated
文件页数: 12/23页
文件大小: 0K
描述: IC LED DRIVER LINEAR 10-UDFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
拓扑: PWM
输出数: 4
内部驱动器:
类型 - 主要: 背光,LED 闪烁器
类型 - 次要: 白色 LED
频率: 1MHz
电源电压: 1.62 V ~ 3.6 V
安装类型: 表面贴装
封装/外壳: 10-WFDFN
供应商设备封装: 10-uDFN(2x2)
包装: 带卷 (TR)
工作温度: -40°C ~ 125°C
SMBus/I 2 C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
PORT_[5]
5-BIT PWM
PORT_[4:0]
0
I/O
CLOCK
3-BIT PRESCALER
CONFIG26 [4:2]
4-BIT BLINK
PORT_[3:0]
1
Figure 2. Output Port Structure
SELECT
INPUT
OUTPUT
V DD
P1
V LA MAX7307 ONLY
PORT P1
SELECT
INPUT
OUTPUT
V DD
P2, P3, P4
V LA MAX7307 ONLY
PORTS P2
THROUGH P4
Figure 3. Port I/O Structure
Port Supplies and Level Translation
The MAX7307 features a port supply, V LA , that provides
the logic supplies to all push-pull I/O ports. P2 through
P4 can be configured as push-pull I/O ports (see Figure
3). V LA powers the logic-high port output voltage sourc-
ing the logic-high port load current. V LA provides level
translation capability for the outputs and operates over a
1.40V to 5.5V voltage independent of the power-supply
voltage, V DD .
Each port of the MAX7307 set as an input can be config-
ured to switch midrail of either the V DD or the V LA port
supplies. Whenever the port supply reference is
changed from V DD to V LA , or vice versa, read the port
register to clear any transition flag on the port.
Ports P2 through P4 are overvoltage protected to V LA .
This is true even for a port used as an input with a V DD
port logic-input threshold. Port P1 is overvoltage pro-
tected to 5.5V, independent of V DD and V LA (see Figure
3). To mix logic outputs with more than one voltage
swing on a group of ports using the same port supply,
set the port supply voltage (V LA ) to be the highest out-
put voltage. Use push-pull outputs and port P1 for the
highest voltage ports, and use open-drain outputs with
external pullup resistors for the lower voltage ports. For
the MAX7307, when P2, P3, and P4 ports are acting as
an input referenced to V DD, make sure the V LA voltage
is greater than V DD - 0.3V.
12
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