参数资料
型号: MAX8620YETD+T
厂商: Maxim Integrated Products
文件页数: 7/18页
文件大小: 0K
描述: IC UPMIC FOR MPU 14-TDFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 微型电源管理集成电路(UPMIC),DSP
输入电压: 2.7 V ~ 5.5 V
输出数: 3
输出电压: 0.6 V ~ 3.3 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 14-WFDFN 裸露焊盘
供应商设备封装: 14-TDFN-EP(3x3)
包装: 带卷 (TR)
μPMIC for Microprocessors or DSPs
in Portable Equipment
Pin Description
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
EP
NAME
SEL1
SEL2
EN2
RESET
BP
HF_PWR
PWR_ON
FB
GND
LX
IN2
IN1
OUT1
OUT2
EP
FUNCTION
LDO Output-Voltage Select Input 1. SEL1 and SEL2 set the OUT1 and OUT2 voltages to one of nine
combinations (Table 1).
LDO Output-Voltage Select Input 2. SEL1 and SEL2 set the OUT1 and OUT2 voltages to one of nine
combinations (Table 1).
OUT2 Enable Input. Drive EN2 low to enable OUT2. Drive EN2 high to disable OUT2. If the MAX8620Y
is placed into shutdown (PWR_ON = HF_PWR = low), OUT2 does not power regardless of the status
of EN2 (Table 2, Figure 4).
Open-Drain, Active-Low Reset Output. RESET asserts low when V OUT1 drops below 87% (typ) of
regulation. RESET remains asserted for t RP after V OUT1 rises above 87% (typ) of regulation. RESET
also asserts when OUT1 is disabled (Figure 4). RESET deasserts if OUT1 is enabled and V OUT1 is
above 87% of regulation after t RP .
Reference Bypass Capacitor Node. Bypass BP with a 0.01μF capacitor to GND. BP is high
impedance when the MAX8620Y is disabled (PWR_ON = HF_PWR = low).
Hands-Free Enable Input. Drive HF_PWR high or apply a pulse to enable the MAX8620Y. Power is
enabled for 1.31s (typ) following a rising edge at HF_PWR (Table 2, Figure 4).
Power-Enable Input. Drive PWR_ON high to enable the MAX8620Y (Table 2, Figure 4). Drive PWR_ON
low to enter shutdown mode. In shutdown, the LX node is high impedance and both LDOs are
disabled (depending on the state of HF_PWR).
Step-Down Converter Output-Voltage Feedback Input. V FB regulates to 0.6V (typ). Connect FB to the
center of an external resistor-divider between LX and GND to set V OUT3 between 0.6V and 3.3V (see
the Setting the Step-Down Output Voltage (OUT3) section).
Ground. Connect GND to the exposed pad.
Inductor Connection. LX is internally connected to the drain of the internal p-channel power MOSFET
and the drain of the n-channel synchronous rectifier. LX is high impedance when OUT3 is disabled.
Power Input 2. Connect IN2 to IN1 as close to the device as possible.
Power Input 1. Connect IN1 to IN2 as close to the device as possible. Bypass IN1 to GND with a 10μF
ceramic capacitor, as close to the device as possible.
300mA LDO Output 1. Bypass OUT1 to GND with a 4.7μF ceramic capacitor for 300mA applications,
or a 2.2μF ceramic capacitor for 150mA applications. OUT1 is high impedance when disabled.
300mA LDO Output 2. Bypass OUT2 to GND with a 4.7μF ceramic capacitor for 300mA applications,
or a 2.2μF ceramic capacitor for 150mA applications. OUT2 is high impedance when disabled.
Exposed Pad. Connect EP to GND.
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