参数资料
型号: MAX8655ETN+T
厂商: Maxim Integrated Products
文件页数: 18/23页
文件大小: 0K
描述: IC REG BUCK ADJ 25A 56TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.7 V ~ 5.5 V
输入电压: 4.5 V ~ 25 V
PWM 型: 电流模式
频率 - 开关: 200kHz ~ 1MHz
电流 - 输出: 25A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 56-WFQFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 56-TQFN-EP(8x8)
Highly Integrated, 25A, Wide-Input,
Internal MOSFET, Step-Down Regulator
inductor and output capacitor resulting in a smaller
phase shift and requiring a less elaborate error-amplifier
compensation than voltage-mode control. A simple
f zMOD =
1
2 π × C OUT × ESR
G MOD ( dc ) = g mc ×
[ ( ]
)
× K S × ( 1 ? D ) ? 0 . 5 ?
? 1 +
series R C and C C is all that is needed to have a stable,
high-bandwidth loop in applications where ceramic
capacitors are used for output filtering. For other types
of capacitors, due to the higher capacitance and ESR,
the frequency of the zero created by the capacitance
and ESR is lower than the desired closed-loop crossover
frequency. To stabilize a nonceramic output-capacitor
loop, add another compensation capacitor from COMP
to GND to cancel this ESR zero. See Figure 9.
The basic regulator loop is modeled as a power modu-
lator, an output feedback divider, and an error amplifi-
er. The power modulator has DC gain G MOD(dc) , set by
g mc x R LOAD , with a pole and zero pair set by R LOAD ,
the output capacitor (C OUT ), and its equivalent series
resistance (ESR). Below are equations that define the
power modulator:
R LOAD
? R LOAD ?
? L × f S ?
where R LOAD = V OUT /I OUT(MAX) , f S is the switching fre-
When C OUT comprises “n” identical capacitors in paral-
lel, the resulting C OUT = n x C OUT(EACH) , and ESR =
ESR (EACH) /n. Note that the capacitor zero for a parallel
combination of like capacitors is the same as for an
individual capacitor. Figure 10 is the simplified gain
plot for the f zMOD > f C case.
The feedback voltage-divider has a gain of G FB =
V FB /V OUT , where V FB is equal to 0.7V.
The transconductance error amplifier has a DC gain,
G EA(DC) = g mEA x R O , where g mEA is the error-amplifi-
er transconductance, which is equal to 110μS, and R O
is the output resistance of the error amplifier, which is
30M ? . A dominant pole (f pdEA ) is set by the compen-
sation capacitor (C C ), the amplifier output resistance
(R O ), and the compensation resistor (R C ); a zero (f zEA )
is set by the compensation resistor (R C ) and the com-
pensation capacitor (C C ). There is an optional pole
(f pEA ) set by C F and R C to cancel the output capacitor
ESR zero if it occurs near the crossover frequency (f C ).
Thus:
quency, L is the output inductance, g mc = 1/(A VCS x
R L ), where A VCS is the gain of the current-sense amplifi-
er (12 typ), R L is the DC resistance of the inductor, the
duty cycle D = V OUT /V IN. K S is a slope compensation
f pdEA =
1
2 π × C C × ( R O + R C )
K S = 1 +
factor calculated from the following equation:
V SCOMP × L × f S
120 × ( V IN ? V OUT ) × R L
When SCOMP is connected to GND, use V SCOMP = 1.25V;
when SCOMP is connected to AVL, use V SCOMP = 2.5V.
Find the pole and zero frequencies created by the
power modulator as follows:
f zEA =
f pEA =
1
2 π × C C × R C
1
2 π × C F × R C
f pMOD =
1
2 π × R LOAD × C OUT
+
× [ K S × ( 1 ? D ) ? 0 . 5 ] ?
?
?
?
1
2 π × L × f S × C OUT
?
?
GAIN
(dB)
POWER
MODULATOR
CLOSED LOOP
ERROR
AMPLIFIER
COMP
fc
MAX8655
R C
C F
0dB
f pMOD
FREQUENCY
FB
C C
DIVIDER
f zMOD
Figure 9. Compensation Components
Figure 10. Simplified Gain Plot for the fzMOD > fC Case
18
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